Abstract: Provided is a processor with a multi-pipeline fetch structure or a multi-cycle cache structure, including: an integer core which reads instruction transmitted from a lower block, executes an operation corresponding to the instruction, and transmits an instruction address to the lower block; an instruction buffer which stores instruction data which are requested by the integer core by using the instruction address and transmits the instruction data in response to the request of the integer core; and an instruction cache which stores a portion of data of a program memory and transmit the data to the instruction buffer in response to the request of the instruction buffer.

Abstract: Provided is a debugging system including: a processor; and a debugger arranged between the processor and an external bus to determine whether or not an address of a job request including an instruction request or a data access request transferred from the processor to the external bus is hit on a preset address, wherein if the address of the job request is hit on the preset address, the debugger does not transfer the job request to the external bus, so that the processor is allowed to be stopped.

Abstract: Provided is an instruction fetch device including a plurality of PC buffers which store addresses of next to-be-executed instructions in respective branches; a plurality of instruction buffers which store to-be-executed instructions and indexes of the PC buffers associated with the respective instructions among the PC buffers; and a fetch unit which fetches the to-be-executed instructions one by one from a program memory to sequentially store the fetched to-be-executed instructions in the instruction buffers and represents the next to-be-executed instruction in a current branch by using the PC buffer hiving one index among the PC buffers before branch prediction is hit, wherein the number of the PC buffers is less than the number of the instruction buffers.

Abstract: Provided is a processor system including: an integer core which reads and processes instructions transmitted from a lower level unit through an external bus and performs an ISR (Interrupt Service Routine) if an interrupt occurs during a process; a data memory which is directly connected to the integer core through no external bus and stores a GPR (General Purpose Register) and an SPR (Special Purpose Register); and a nested vectored interrupt controller (NVIC) which is directly connected to the integer core and the data memory through no external bus, performs backup of the GPR and SPR from the integer core if an interrupt occurs during the process, and controls an interrupt operation in a manner that the backup GPR and SPR are transmitted to the data memory.

Abstract: Provided is a method of decoding instructions in a microprocessor, including: checking existence of instructions when instruction decoding is stared; folding two instructions when two instructions exist; and decoding folded instructions. Accordingly, it is possible to improve performance in a microprocessor by generating one instruction by folding two instructions into one instruction in an instruction decoding period.

Abstract: Provided is a processor with a multi-pipeline fetch structure or a multi-cycle cache structure, including: an integer core which reads instruction transmitted from a lower block, executes an operation corresponding to the instruction, and transmits an instruction address to the lower block; an instruction buffer which stores instruction data which are requested by the integer core by using the instruction address and transmits the instruction data in response to the request of the integer core; and an instruction cache which stores a portion of data of a program memory and transmit the data to the instruction buffer in response to the request of the instruction buffer.

Abstract: The present invention relates to a decoding method for a raptor codes using system, which is capable of improving performance of the system and limiting increase in the amount of computation by grouping variable nodes if raptor codes are unsuccessfully decoded, to thereby increase a conjecture efficiency of variable node values. The decoding method is capable of improving performance of the system by making it possible to achieve performance improvement and additional reduction of the amount of computation even under an application of MP decoding by grouping variable nodes whose values cannot be known when decoded, dividing groups of variable nodes into sub groups, and conjecturing and recovering the variable nodes in a manner to exclude sub groups which do not satisfy check node equation.

Abstract: A Multiple-Input Multiple-Output (MIMO) relay system is provided. The MIMO relay system performs signal processing to provide requested real data to at least one selected user mobile station sequentially connected to a first relay station located in a first cell and a second relay station located in a second cell using spare frequency capacity allocated to a first base station of the first cell instead of a second base station of the second cell that drops the requested real data due to its frequency capacity being exceeded, thereby improving reliability of seamless real data input/output in relay communication, reducing call drop probability, and raising availability of frequency capacity by automatically adjusting frequency capacity allocated between cells.

Abstract: A multi-coexistence communication technology is provided. A multi-coexistence communication system based on an interference-aware environment and a method for operating the same can remove interference detected using an interference temperature limit from at least one transmission signal and transmit the signal to a main/sub communication terminal during data communication on a wired/wireless communication network formed of a main base station, a sub base station, the main communication terminal, and the sub communication terminal, thereby smoothly providing a high-speed seamless data transmission service based on a multi-coexistence communication environment where a distributed small-scale network requiring a low transmission rate, a medium-scale network for providing various wireless communication services, and a large-scale broadcasting network requiring a high transmission rate and high quality coexist, and preventing congestion due to increased demand for frequency resources.

Abstract: A block interleaving apparatus for block interleaving M-bit input streams to be transferred with a modulus k using a mixed radix system in a multi-band orthogonal frequency division multiplexing communication system, including an array processor having an array including M cells in which the number of columns is k and the number of rows is M/k. The array processor inputs the input streams from the bottom-right cell up to the top-left last cell in the horizontal direction, and, after the first bit of the input streams reaches the last cell, generates interleaved output streams by changing the output of the array processor from horizontal direction to vertical direction.

Abstract: A block interleaving apparatus for block interleaving M-bit input streams to be transferred with a modulus k using a mixed radix system in a multi-band orthogonal frequency division multiplexing communication system, including an array processor having an array including M cells in which the number of columns is k and the number of rows is M/k. The array processor inputs the input streams from the bottom-right cell up to the top-left last cell in the horizontal direction, and, after the first bit of the input streams reaches the last cell, generates interleaved output streams by changing the output of the array processor from horizontal direction to vertical direction.

Abstract: Disclosed is a method for detecting a symbol using a trellis structure on a multiple input multiple output (MIMO) mobile communication system. The method includes the steps of: setting a plurality of states by grouping symbols producible from a receiving signal in the unit of sub-states; calculating metric values for paths inputted to the sub-states and selecting paths having the calculated metric values smaller than a preset first threshold, as first surviving paths; setting a second threshold based on an accumulated metric value of a path having the smallest accumulated metric in each of the states; and selecting paths having metric value smaller than the second threshold, as second surviving paths, among the first surviving paths selected for each state.

Abstract: An apparatus includes an instruction word storage for storing a plurality of general instruction words and extended instruction words, a temporary storage unit including a plurality of buffers for pre-fetching and storing the plurality of instruction words from the instruction word storage, an instruction word search unit for receiving and decoding the plurality of instruction words pre-fetched and outputting a position signal of a general instruction word and the positions of one or more successive extended instruction words stored in the temporary storage a selector for selecting a buffer in which a general instruction word is stored and outputting the general instruction word sequentially, according to the position signal a general instruction word parser for receiving a general instruction word from the selector and outputting a plurality of control signals for executing the general instruction word simultaneously, an extended data parser is provided for performing an operational processing of operands of

Abstract: A graphics subsystem utilizes a single port DRAM as a frame buffer, which has an r-bit wide data access port and stores video data that are generated by an application program executed on a host processor. The graphics subsystem includes a first-in first-out (FIFO) buffer for storing the video data from the frame buffer, and a scan interpolator for performing vertical and horizontal interpolation of data read from the FIFO buffer with respect to a predetermined number of adjacent scan lines on a video frame. By interpolating adjacent scan lines in real time, it is possible to obtain high-quality images on a computer or television display.