Patents by Inventor Byung-Ho Kwak

Byung-Ho Kwak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10366797
    Abstract: Disclosed are a system and method for preventing and monitoring a leakage of water from a tank liner at a storage tank having: a concrete reservoir; the tank liner made up of a wall liner that is formed by coupling a plurality of first panels and is attached to an inner wall of the concrete reservoir, and a floor liner that is formed by coupling a plurality of second panels, is attached to a floor of the concrete reservoir, and is coupled to the wall liner by welding; a leaking water collecting plate formed by welding a plurality of third panels and inserted between the floor liner and the floor of the concrete reservoir; and an edge leaking water collecting channel buried in an edge of the storage tank and configured to collect leaking water discharged between the floor liner and the leaking water collecting plate.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: July 30, 2019
    Assignee: Korea Atomic Energy Research Institute
    Inventors: Jong Min Lee, Byung Ho Kwak, Un-Soo Jung, Jeong-Soo Ryu
  • Publication number: 20170221592
    Abstract: Disclosed are a system and method for preventing and monitoring a leakage of water from a tank liner at a storage tank having: a concrete reservoir; the tank liner made up of a wall liner that is formed by coupling a plurality of first panels and is attached to an inner wall of the concrete reservoir, and a floor liner that is formed by coupling a plurality of second panels, is attached to a floor of the concrete reservoir, and is coupled to the wall liner by welding; a leaking water collecting plate formed by welding a plurality of third panels and inserted between the floor liner and the floor of the concrete reservoir; and an edge leaking water collecting channel buried in an edge of the storage tank and configured to collect leaking water discharged between the floor liner and the leaking water collecting plate.
    Type: Application
    Filed: November 11, 2016
    Publication date: August 3, 2017
    Applicant: KOREA ATOMIC ENERGY RESEARCH INSTITUTE
    Inventors: Jong Min LEE, Byung Ho KWAK, Un-Soo JUNG, Jeong-Soo RYU
  • Patent number: 9390961
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a first bit line structure extending in a first direction, a second bit line structure extending in the first direction and spaced apart from the first bit line structure, a storage contact plug located between the first bit line structure and the second bit line structure, and extending in a second direction perpendicular to the first direction, a first plug insulator located between the first bit line structure and the second bit line structure, and configured to contact a side surface extending in the second direction of the storage contact plug, and a plug isolation pattern located between the first bit line structure and the first plug insulator.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: July 12, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mong-Sup Lee, Byoung-Yong Gwak, Byung-Ho Kwak, Yoon-Kyung Kim, Tae-Joon Park, Byung-Sul Ryu, In-Seak Hwang
  • Publication number: 20150171163
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a first bit line structure extending in a first direction, a second bit line structure extending in the first direction and spaced apart from the first bit line structure, a storage contact plug located between the first bit line structure and the second bit line structure, and extending in a second direction perpendicular to the first direction, a first plug insulator located between the first bit line structure and the second bit line structure, and configured to contact a side surface extending in the second direction of the storage contact plug, and a plug isolation pattern located between the first bit line structure and the first plug insulator.
    Type: Application
    Filed: September 10, 2014
    Publication date: June 18, 2015
    Inventors: Mong-Sup LEE, Byoung-Yong GWAK, Byung-Ho KWAK, Yoon-Kyung KIM, Tae-Joon PARK, Byung-Sul RYU, In-Seak HWANG
  • Patent number: 7476614
    Abstract: A method of fabricating a semiconductor device comprises sequentially forming a first conductive layer, a first insulating interlayer, a second conductive layer, and a second insulating interlayer on a semiconductor substrate. A mask layer is formed on the second insulating interlayer, and then the second insulating interlayer, the second conductive layer, and the first insulating interlayer are selectively removed using the mask layer as an etch mask to form a contact hole exposing the first conductive layer. Portions of the second conductive layer exposed in sidewalls of the contact hole are then selectively etched to form a recess between the first and second insulating interlayers. Next, a third conductive layer is formed on a bottom surface and on sidewalls of the contact hole, a metal silicide layer is formed to fill the recess, and a fourth conductive layer is formed to fill the contact hole over the metal silicide layer.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: January 13, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Ho Kwak, Bum-Soo Chang
  • Publication number: 20070032074
    Abstract: A method of fabricating a semiconductor device comprises sequentially forming a first conductive layer, a first insulating interlayer, a second conductive layer, and a second insulating interlayer on a semiconductor substrate. A mask layer is formed on the second insulating interlayer, and then the second insulating interlayer, the second conductive layer, and the first insulating interlayer are selectively removed using the mask layer as an etch mask to form a contact hole exposing the first conductive layer. Portions of the second conductive layer exposed in sidewalls of the contact hole are then selectively etched to form a recess between the first and second insulating interlayers. Next, a third conductive layer is formed on a bottom surface and on sidewalls of the contact hole, a metal silicide layer is formed to fill the recess, and a fourth conductive layer is formed to fill the contact hole over the metal silicide layer.
    Type: Application
    Filed: July 24, 2006
    Publication date: February 8, 2007
    Inventors: Byung-Ho Kwak, Bum-Soo Chang