Patents by Inventor Byung-Hong Chung
Byung-Hong Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9553141Abstract: A semiconductor device includes a plurality of lower electrodes having a vertical length greater than a horizontal width on a substrate, a supporter disposed between the lower electrodes, an upper electrode disposed on the lower electrodes, and a capacitor dielectric layer disposed between the lower electrodes and the upper electrode. The supporter includes a first element, a second element, and oxygen, an oxide of the second element has a higher band gap energy than an oxide of the first element, and the content of the second element in the supporter is from about 10 at % to 90 at %.Type: GrantFiled: September 18, 2015Date of Patent: January 24, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Jeong Yang, Soon-Wook Jung, Bong-Jin Kuh, Wan-Don Kim, Byung-Hong Chung, Yong-Suk Tak
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Publication number: 20160005806Abstract: A semiconductor device includes a plurality of lower electrodes having a vertical length greater than a horizontal width on a substrate, a supporter disposed between the lower electrodes, an upper electrode disposed on the lower electrodes, and a capacitor dielectric layer disposed between the lower electrodes and the upper electrode. The supporter includes a first element, a second element, and oxygen, an oxide of the second element has a higher band gap energy than an oxide of the first element, and the content of the second element in the supporter is from about 10 at % to 90 at %.Type: ApplicationFiled: September 18, 2015Publication date: January 7, 2016Inventors: Hyun-Jeong YANG, Soon-Wook JUNG, Bong-Jin KUH, Wan-Don KIM, Byung-Hong CHUNG, Yong-Suk TAK
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Patent number: 9142558Abstract: A semiconductor device includes a plurality of lower electrodes having a vertical length greater than a horizontal width on a substrate, a supporter disposed between the lower electrodes, an upper electrode disposed on the lower electrodes, and a capacitor dielectric layer disposed between the lower electrodes and the upper electrode. The supporter includes a first element, a second element, and oxygen, an oxide of the second element has a higher band gap energy than an oxide of the first element, and the content of the second element in the supporter is from about 10 at % to 90 at %.Type: GrantFiled: October 29, 2013Date of Patent: September 22, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Jeong Yang, Soon-Wook Jung, Bong-Jin Kuh, Wan-Don Kim, Byung-Hong Chung, Yong-Suk Tak
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Patent number: 8970039Abstract: A semiconductor device includes a plurality of electrode structures perpendicularly extending on a substrate, and at least one support unit extending between the plurality of electrode structures. The support unit includes at least one support layer including a noncrystalline metal oxide contacting a part of the plurality of electrode structures. Related devices and fabrication methods are also discussed.Type: GrantFiled: December 6, 2012Date of Patent: March 3, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Bong-jin Kuh, Sang-ryol Yang, Soon-wook Jung, Young-sub You, Byung-hong Chung, Han-mei Choi, Jong-sung Lim
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Patent number: 8889560Abstract: Methods of forming fine patterns for a semiconductor device include forming a hard mask layer on an etch target layer; forming a carbon containing layer on the hard mask layer; forming carbon containing layer patterns by etching the carbon containing layer; forming spacers covering opposing side walls of each of the carbon containing layer patterns; removing the carbon containing layer patterns; forming hard mask patterns by etching the hard mask layer using the spacers as a first etching mask; and etching the etch target layer by using the hard mask patterns a second etching mask.Type: GrantFiled: May 18, 2012Date of Patent: November 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-hong Chung, Cha-young Yoo, Dong-hyun Kim
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Publication number: 20140138794Abstract: A semiconductor device includes a plurality of lower electrodes having a vertical length greater than a horizontal width on a substrate, a supporter disposed between the lower electrodes, an upper electrode disposed on the lower electrodes, and a capacitor dielectric layer disposed between the lower electrodes and the upper electrode. The supporter includes a first element, a second element, and oxygen, an oxide of the second element has a higher band gap energy than an oxide of the first element, and the content of the second element in the supporter is from about 10 at % to 90 at %.Type: ApplicationFiled: October 29, 2013Publication date: May 22, 2014Inventors: Hyun-Jeong YANG, Soon-Wook JUNG, Bong-Jin KUH, Wan-Don KIM, Byung-Hong CHUNG, Yong-Suk TAK
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Patent number: 8642458Abstract: A method of fabricating a nonvolatile memory device includes providing an intermediate structure in which a floating gate and an isolation film are disposed adjacent to each other on a semiconductor substrate and a gate insulating film is disposed on the floating gate and the isolation film, forming a conductive film on the gate insulating film, and annealing the conductive film so that part of the conductive film on an upper portion of the floating gate flows down onto a lower portion of the floating gate and an upper portion of the isolation film.Type: GrantFiled: March 7, 2012Date of Patent: February 4, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Hong Chung, Young-Hee Kim, In-Sun Yi, Han-Mei Choi
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Publication number: 20130034963Abstract: Methods of forming fine patterns for a semiconductor device include forming a hard mask layer on an etch target layer; forming a carbon containing layer on the hard mask layer; forming carbon containing layer patterns by etching the carbon containing layer; forming spacers covering opposing side walls of each of the carbon containing layer patterns; removing the carbon containing layer patterns; forming hard mask patterns by etching the hard mask layer using the spacers as a first etching mask; and etching the etch target layer by using the hard mask patterns a second etching mask.Type: ApplicationFiled: May 18, 2012Publication date: February 7, 2013Inventors: Byung-hong Chung, Cha-young Yoo, Dong-hyun Kim
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Publication number: 20120315752Abstract: A method of fabricating a nonvolatile memory device includes providing an intermediate structure in which a floating gate and an isolation film are disposed adjacent to each other on a semiconductor substrate and a gate insulating film is disposed on the floating gate and the isolation film, forming a conductive film on the gate insulating film, and annealing the conductive film so that part of the conductive film on an upper portion of the floating gate flows down onto a lower portion of the floating gate and an upper portion of the isolation film.Type: ApplicationFiled: March 7, 2012Publication date: December 13, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byung-Hong CHUNG, Young-Hee KIM, In-Sun YI, Han-Mei CHOI
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Patent number: 7951671Abstract: A method of fabricating a non-volatile memory device includes forming an isolation trench in a semiconductor substrate, and the isolation trench defines first and second fins. The method further includes forming an isolation layer partially filling the isolation trench, forming first and second charge trap patterns respectively covering parts of the first and second fins projecting from the isolation layer, and forming a control gate electrode covering the first and second charge trap patterns and crossing the first and second fins.Type: GrantFiled: May 11, 2009Date of Patent: May 31, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Wan Lim, Hyun-Seok Jang, Byung-Hong Chung, Ki-Hyun Hwang, Sang-Ryol Yang
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Patent number: 7829437Abstract: In a method of manufacturing a semiconductor device, a first substrate and a second substrate, which include a plurality of memory cells and selection transistors, respectively, are provided. A first insulating interlayer and a second insulating interlayer are formed on the first substrate and the second substrate, respectively, to cover the memory cells and the selection transistors. A lower surface of the second substrate is partially removed to reduce a thickness of the second substrate. The lower surface of the second substrate is attached to the first insulating interlayer. Plugs are formed through the second insulating interlayer, the second substrate and the first insulating interlayer to electrically connect the selection transistors in the first substrate and the second substrate to the plugs. Thus, impurity ions in the first substrate will not diffuse during a thermal treatment process.Type: GrantFiled: June 16, 2008Date of Patent: November 9, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hoo Kim, Hyun Park, Byung-Hong Chung, Jeong-Lim Nam
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Patent number: 7745325Abstract: A wiring structure of a semiconductor device may include an insulation interlayer on a substrate, the insulation interlayer having a linear first trench having a first width and a linear second trench having a second width, the linear second trench being in communication with a lower portion of the linear first trench, the first width being wider than the second width, and a conductive layer pattern in the linear first and second trenches.Type: GrantFiled: May 16, 2007Date of Patent: June 29, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Ho Koh, Byung-Hong Chung, Won-Jin Kim, Hyun Park, Ji-Young Min
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Patent number: 7678650Abstract: Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.Type: GrantFiled: May 20, 2009Date of Patent: March 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Cha-Won Koh, Byung-Hong Chung, Sang-Gyun Woo, Jeong-Lim Nam, Seok-Hwan Oh, Jai-Hyuk Song, Hyun Park, Yool Kang
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Publication number: 20090258473Abstract: Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.Type: ApplicationFiled: May 20, 2009Publication date: October 15, 2009Inventors: Cha-Won Koh, Byung-Hong Chung, Sang-Gyun Woo, Jeong-Lim Nam, Seok-Hwan Oh, Jai-Hyuk Song, Hyun Park, Yool Kang
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Publication number: 20090221140Abstract: A non-volatile memory device prevents charge spreading. The non-volatile memory device includes an isolation trench in a semiconductor substrate, an isolation layer partially filling the isolation trench between first and second fins defined by the isolation trench, a control gate electrode crossing the first and second fins, a first charge trap pattern between the first fin and the control gate electrode, and a second charge trap pattern between the second fin and the control gate electrode.Type: ApplicationFiled: May 11, 2009Publication date: September 3, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Wan Lim, Hyun-Seok Jang, Byung-Hong Chung, Ki-Hyun Hwang, Sang-Ryol Yang
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Patent number: 7560768Abstract: Provided are a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.Type: GrantFiled: November 9, 2006Date of Patent: July 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Cha-Won Koh, Byung-Hong Chung, Sang-Gyun Woo, Jeong-Lim Nam, Seok-Hwan Oh, Jai-Hyuk Song, Hyun Park, Yool Kang
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Publication number: 20090004826Abstract: In a method of manufacturing a semiconductor device, a first substrate and a second substrate, which include a plurality of memory cells and selection transistors, respectively, are provided. A first insulating interlayer and a second insulating interlayer are formed on the first substrate and the second substrate, respectively, to cover the memory cells and the selection transistors. A lower surface of the second substrate is partially removed to reduce a thickness of the second substrate. The lower surface of the second substrate is attached to the first insulating interlayer. Plugs are formed through the second insulating interlayer, the second substrate and the first insulating interlayer to electrically connect the selection transistors in the first substrate and the second substrate to the plugs. Thus, impurity ions in the first substrate will not diffuse during a thermal treatment process.Type: ApplicationFiled: June 16, 2008Publication date: January 1, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Hoo Kim, Hyun Park, Byung-Hong Chung, Jeong-Lim Nam
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Publication number: 20080207503Abstract: The present disclosure demonstrates that cholesterol-free discoidal reconstituted HDL (R-HDL), phosphatidyl-choline (PC) and PC liposomes effectively released cholesterol from ICP. Native HDL and its apolipoproteins were not able to release cholesterol from ICP. The release of ICP cholesterol by R-HDL was dose-dependent and accompanied by the transfer of >8× more PC in the reverse direction (i.e., from R-HDL to ICP), resulting in a marked enrichment of ICP with PC. The enrichment of ICP with PC resulted in the dissolution of cholesterol crystals on ICP and allowed the removal of ICP cholesterol by apo HDL and plasma. The present disclosure provides a method of treatment for removal of cholesterol from ICP in vivo and compositions for use in such method of treatment. Such methods may be used in the treatment and/or prevention of atherosclerosis, coronary artery disease, and related disease states and conditions.Type: ApplicationFiled: December 22, 2005Publication date: August 28, 2008Inventors: Byung-Hong Chung, Byung Hui Cho
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Publication number: 20080105919Abstract: A non-volatile memory device prevents charge spreading. The non-volatile memory device includes an isolation trench in a semiconductor substrate, an isolation layer partially filling the isolation trench between first and second fins defined by the isolation trench, a control gate electrode crossing the first and second fins, a first charge trap pattern between the first fin and the control gate electrode, and a second charge trap pattern between the second fin and the control gate electrode.Type: ApplicationFiled: June 29, 2007Publication date: May 8, 2008Inventors: Ju-Wan Lim, Hyun-Seok Jang, Byung-Hong Chung, Ki-Hyun Hwang, Sang-Ryol Yang
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Publication number: 20080017889Abstract: A wiring structure of a semiconductor device may include an insulation interlayer on a substrate, the insulation interlayer having a linear first trench having a first width and a linear second trench having a second width, the linear second trench being in communication with a lower portion of the linear first trench, the first width being wider than the second width, and a conductive layer pattern in the linear first and second trenches.Type: ApplicationFiled: May 16, 2007Publication date: January 24, 2008Inventors: Young-Ho Koh, Byung-Hong Chung, Won-Jin Kim, Hyun Park, Ji-Young Min