Abstract: A source driver control device and method. The source driver control device includes a memory, a first write controller, a second write controller and a write clock signal generator. The memory receives display data corresponding to an image and stores the display data in response to a write clock signal. The first write controller generates a first write enable signal in response to a vertical back porch and a horizontal back porch. The second write controller generates a second write enable signal, which is enabled for each write cycle of storing the display data in the memory, in response to the first write enable signal. The write clock signal generator generates the write clock signal in a period in which the second write enable signal is enabled. The write cycle corresponds to a multiple of a reference write cycle. The source driver control device and method can reduce power consumed when the display data is written in the memory.

Abstract: A display device includes a display panel having a plurality of scan lines and a plurality of data lines, and a plurality of display panel driving apparatuses. Each of the display panel driving apparatuses includes a data line driving circuit, and a plurality of pads via which corresponding gray-scale voltages are respectively output. The data line driving circuit drives corresponding data lines of the plurality of the data lines. Each of the plurality of the pads outputs a corresponding gray-scale voltage of a plurality of gray-scale voltages, wherein the pads of the display panel driving apparatuses are connected in a cascade. The pads of the display panel driving apparatuses may be connected via a flexible printed circuit.

Abstract: Provided are a level shifter circuit and a corresponding method for controlling voltage levels of a clock signal and an inverted clock signal for driving gate lines of a ASG thin film transistor liquid crystal display panel, where the level shifter circuit includes first and second level shifters, the first level shifter controls the voltage level of the clock signal to swing between a negative external voltage level and a positive external voltage level in response to a clock activating signal, and increases the voltage level of the clock signal from the negative external voltage level to a power supply voltage level or decreases it from the positive external voltage level to a ground voltage level while a pre-charge clock activating signal is activated, the second level shifter controls the voltage level of the inverted clock signal to swing between the negative external voltage level and the positive external voltage level in response to an inverted clock activating signal, and increases the voltage level

Abstract: An output buffer capable of reducing the noise and distortion of buffered output data while operating at high speed, and a buffering method performed in the output buffer are provided. An output buffer for buffering input data and outputting buffered input data as output data comprises first through M-th and (M+1)th through (M+N)th delay means for delaying the input data for (M+N) different delay times and outputting one by one delayed data in a predetermined order at time intervals of T M + N , where M and N are each integers equal to or greater than 2, and T corresponds to the time necessary for the level of the output data to change, and a data output means for outputting the output data in response to the outputs of the first through (M+N)th delay means.

Abstract: A differential delay circuit type ring oscillator allows for an increase in operation enabling frequency and dynamic range. At each stage of the ring, delay circuit output signals arc linearly varied above and below the circuit switching level. The ring oscillator includes a plurality of differential delay circuits coupled in series in a ring configuration, a differential amplifier, and a comparator. Each of the differential delay circuits receives first and second differential input signals, and delays the received signals by a predetermined time in response to a predetermined control signal to generate first and second differential output signals. The differential amplifier receives the first and the second differential output signals of one of the differential delay circuits and amplifies the received signals to generate first and second differential amplified signals.