Patents by Inventor Byung Hun Min
Byung Hun Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9306777Abstract: A direct conversion receiver includes: a high linearity mixer device including a sampler unit charge-sampling an input current according to a sampling frequency, and a buffer unit receiving an output signal from the sampler unit while having a low input impedance, amplifying the received signal, and outputting a current signal; and a filter device decimating an output signal from the mixer device and FIR-filtering the decimated signal.Type: GrantFiled: February 18, 2014Date of Patent: April 5, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jung Woo Park, Young Jae Lee, Hyun Kyu Yu, Byung Hun Min, Seong Do Kim, Hoai Nam Nguyen, Sang Gug Lee
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Patent number: 9013216Abstract: Disclosed is a digital phase-locked-loop including: a time-to-digital converter (TDC) configured to output a digital bit based on an input clock and a reference clock, in which the TDC includes: a first arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a first average offset and output a first logic value; a second arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a second average offset and output a second logic value; and a signal processor configured to output the digital bit based on the first and second logic values.Type: GrantFiled: September 17, 2013Date of Patent: April 21, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Hyun Ho Boo, Byung Hun Min, Duong Quoc Hoang, Cheon Soo Kim, Hyun Kyu Yu
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Publication number: 20140266354Abstract: Disclosed is a digital phase-locked-loop including: a time-to-digital converter (TDC) configured to output a digital bit based on an input clock and a reference clock, in which the TDC includes: a first arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a first average offset and output a first logic value; a second arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a second average offset and output a second logic value; and a signal processor configured to output the digital bit based on the first and second logic values.Type: ApplicationFiled: September 17, 2013Publication date: September 18, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Hyun Ho BOO, Byung Hun MIN, Duong Quoc HOANG, Cheon Soo KIM, Hyun Kyu YU
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Publication number: 20140169512Abstract: A direct conversion receiver includes: a high linearity mixer device including a sampler unit charge-sampling an input current according to a sampling frequency, and a buffer unit receiving an output signal from the sampler unit while having a low input impedance, amplifying the received signal, and outputting a current signal; and a filter device decimating an output signal from the mixer device and FIR-filtering the decimated signal.Type: ApplicationFiled: February 18, 2014Publication date: June 19, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Jung Woo PARK, Young Jae LEE, Hyun Kyu Yu, Byung Hun MIN, Seong Do KIM, Hoai Nam NGUYEN, Sang Gug LEE
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Patent number: 8611466Abstract: Provided is a discrete time receiver having a structure capable of processing various broadband signals. The discrete time receiver uses a discrete time filter having a sampling frequency in a constant range so as to process a signal having an input frequency in a wide range and a wide bandwidth, so that it is possible to reduce current consumption and the area of the discrete time receiver. Since the discrete time receiver is easily integrated with a digital device, it is easy to design a chip using system on chip (SoC).Type: GrantFiled: December 2, 2011Date of Patent: December 17, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Young-Jae Lee, Byung Hun Min, Nguyen Hoai Nam
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Patent number: 8258832Abstract: Provided is a loop filter which receives first and second currents whose current ratio is n (where n is a natural number). The loop filter includes a first-order filter path, a second-order filter path, and a third-order filter path. The first-order filter path includes an operational amplifier generating an output impedance by increasing by as much as n times an impedance of a second input node to which the second current is applied. The first-order filter path performs a first-order filtering on the first current applied to a first input node by using the operational amplifier. The second-order filter path performs a second-order filtering on the first current applied to the first input node. The third-order filter path performs a third-order filtering on the first current applied to the first input node.Type: GrantFiled: August 20, 2010Date of Patent: September 4, 2012Assignee: Electronics and Telecommunications Research InstituteInventor: Byung Hun Min
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Publication number: 20120170694Abstract: Provided is a discrete time receiver having a structure capable of processing various broadband signals. The discrete time receiver uses a discrete time filter having a sampling frequency in a constant range so as to process a signal having an input frequency in a wide range and a wide bandwidth, so that it is possible to reduce current consumption and the area of the discrete time receiver. Since the discrete time receiver is easily integrated with a digital device, it is easy to design a chip using system on chip (SoC).Type: ApplicationFiled: December 2, 2011Publication date: July 5, 2012Applicant: Electronics and Telecommunications Research InstituteInventors: Young-Jae LEE, Byung Hun Min, Nguyen Hoai Nam
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Patent number: 8193842Abstract: There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency.Type: GrantFiled: January 5, 2012Date of Patent: June 5, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Byung Hun Min, Hyun Kyu Yu
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Publication number: 20120105116Abstract: There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency.Type: ApplicationFiled: January 5, 2012Publication date: May 3, 2012Applicant: Electronics and Telecommunications Research InstituteInventors: Byung Hun MIN, Hyun Kyu Yu
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Patent number: 8115525Abstract: There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency.Type: GrantFiled: November 25, 2009Date of Patent: February 14, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Byung Hun Min, Hyun Kyu Yu
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Patent number: 8031009Abstract: A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting an oscillation frequency of an oscillation signal according to a control value; a programmable divider dividing the oscillation signal according to a division ratio to output a divided signal; a counter counting the number of clocks of the divided signal for one cycle of a reference signal to output a count value; and a frequency detector obtaining the control value by subtracting the count value from a reference comparison value, wherein the reference comparison value is obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider.Type: GrantFiled: October 16, 2009Date of Patent: October 4, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Byung Hun Min, Ja Yol Lee, Seong Do Kim, Cheon Soo Kim, Hyun Kyu Yu
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Patent number: 7999707Abstract: An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N?1)th fragmented delay phases; an adding unit adding each of the first to the (N?1)th fragmented delay phases to the phase error to generate first to (N?1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N?1)th phase errors.Type: GrantFiled: December 1, 2009Date of Patent: August 16, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Mi Jeong Park, Byung Hun Min, Ja Yol Lee, Hyun Kyu Yu
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Publication number: 20110150138Abstract: A direct conversion receiver includes: a high linearity mixer device including a sampler unit charge-sampling an input current according to a sampling frequency, and a buffer unit receiving an output signal from the sampler unit while having a low input impedance, amplifying the received signal, and outputting a current signal; and a filter device decimating an output signal from the mixer device and FIR-filtering the decimated signal.Type: ApplicationFiled: December 16, 2010Publication date: June 23, 2011Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jung Woo PARK, Young Jae Lee, Hyun Kyu Yu, Byung Hun Min, Seong Do Kim, Hoai Nam Nguyen, Sang Gug Lee
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Patent number: 7961038Abstract: A digital proportional integral loop filter is provided. A first proportional amplification unit multiplies a phase error value by a first proportional loop gain, and a first integral amplification unit multiplies a phase error accumulation value by a first integral loop gain. A second proportional amplification unit multiplies the phase error value by a second proportional loop gain, and a second integral amplification unit multiplies the phase error accumulation value by a second integral loop gain. A first offset value generation unit generates a first offset value by subtracting the second proportional loop gain from the first proportional loop gain and multiplying a resulting value by a phase error average value, and a second offset value generation unit generates a second offset value by subtracting the second integral loop gain from the first integral loop gain and multiplying a resulting value by a phase error accumulation average value.Type: GrantFiled: December 4, 2009Date of Patent: June 14, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Mi Jeong Park, Byung Hun Min, Ja Yol Lee, Hyun Kyu Yu
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Publication number: 20110115535Abstract: Provided is a loop filter which receives first and second currents whose current ratio is n (where n is a natural number). The loop filter includes a first-order filter path, a second-order filter path, and a third-order filter path. The first-order filter path includes an operational amplifier generating an output impedance by increasing by as much as n times an impedance of a second input node to which the second current is applied. The first-order filter path performs a first-order filtering on the first current applied to a first input node by using the operational amplifier. The second-order filter path performs a second-order filtering on the first current applied to the first input node. The third-order filter path performs a third-order filtering on the first current applied to the first input node.Type: ApplicationFiled: August 20, 2010Publication date: May 19, 2011Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventor: Byung Hun MIN
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Publication number: 20100145482Abstract: A digital proportional integral loop filter is provided. A first proportional amplification unit multiplies a phase error value by a first proportional loop gain, and a first integral amplification unit multiplies a phase error accumulation value by a first integral loop gain. A second proportional amplification unit multiplies the phase error value by a second proportional loop gain, and a second integral amplification unit multiplies the phase error accumulation value by a second integral loop gain. A first offset value generation unit generates a first offset value by subtracting the second proportional loop gain from the first proportional loop gain and multiplying a resulting value by a phase error average value, and a second offset value generation unit generates a second offset value by subtracting the second integral loop gain from the first integral loop gain and multiplying a resulting value by a phase error accumulation average value.Type: ApplicationFiled: December 4, 2009Publication date: June 10, 2010Applicant: Electronics and Telecommunications Research InstituteInventors: Mi jeong PARK, Byung Hun Min, Ja Yol Lee, Hyun Kyu Yu
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Publication number: 20100134160Abstract: There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency.Type: ApplicationFiled: November 25, 2009Publication date: June 3, 2010Applicant: Electronics and Telecommunications Research InstituteInventors: Byung Hun MIN, Hyun Kyu YU
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Publication number: 20100134335Abstract: An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N?1)th fragmented delay phases; an adding unit adding each of the first to the (N?1)th fragmented delay phases to the phase error to generate first to (N?1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N?1)th phase errors.Type: ApplicationFiled: December 1, 2009Publication date: June 3, 2010Applicant: Electronics and Telecommunications Research InstituteInventors: Mi Jeong Park, Byung Hun Min, Ja Yol Lee, Hyun Kyu Yu
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Publication number: 20100134195Abstract: There is provided a capacitor having variable capacitance, which forms different capacitances according to a control signal by applying a switch to a metal-oxide-metal (MOM) structure plate capacitor using a CMOS process. The capacitor includes a stack structure including a plurality of metal layers including a first metal layer, and a plurality of dielectric layers respectively interposed between the plurality of metal layers, and a switch part including at least one switch having one side connected to at least one metal layer among the plurality of metal layers other than the first metal layer. The first metal layer and the other side of the switch serve as both terminals of the capacitor, and at least two capacitances are provided between both terminals of the capacitor upon controlling a short/open of the switch.Type: ApplicationFiled: December 2, 2009Publication date: June 3, 2010Applicant: Electronics and Telecommunications Research InstituteInventors: Ja Yol LEE, Byung Hun Min, Seong Do Kim, Hyun Kyu Yu
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Publication number: 20100134192Abstract: A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting a oscillation frequency according to control value; a programmable divider dividing the oscillation frequency according to a division ratio; a counter counting the number of clocks of the divided frequency by using a reference frequency; and a frequency detector outputting a value obtained by subtracting the number of the counted clocks from a reference comparison value, a value obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider, as the control value of the oscillator.Type: ApplicationFiled: October 16, 2009Publication date: June 3, 2010Applicant: Electronics and Telecommunications Research InstituteInventors: Byung Hun MIN, Ja Yol Lee, Seong Do Kim, Cheon Soo Kim, Hyun Kyu Yu