Abstract: A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programmable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.

Abstract: A memory device includes a first semiconductor structure including pass transistors defined in a row decoder region of a substrate, a first bonding layer including first bonding pads, and bottom wiring layers disposed between the substrate and the first bonding layer; a second semiconductor structure including a second bonding layer including second bonding pads bonded to the first bonding pads, a memory cell array, and a top wiring layer disposed between the second bonding layer and the memory cell array; and global lines disposed in the row decoder region, and configured to transfer operating voltages to the pass transistors, wherein the bottom wiring layers include bottom wiring layers of a first tier and bottom wiring layers of a second tier disposed over the bottom wiring layers of the first tier, and the global lines are disposed in at least one of the bottom wiring layers of the first tier.

Abstract: A memory device includes a substrate defined with a first cell region and a second cell region, and a row decoder region between the first and second cell regions; a peripheral circuit defined in the first and second cell regions of the substrate; pass transistors defined in the row decoder region of the substrate; bottom wiring layers disposed in a first dielectric layer covering the peripheral circuit and the pass transistors; a memory cell array defined on the first dielectric layer; a second dielectric layer defined on the first dielectric layer, and covering the memory cell array; top wiring layers disposed in a third dielectric layer defined on the second dielectric layer; and global lines disposed in the row decoder region, and configured to transfer operating voltages to the pass transistors, wherein the global lines are disposed only in at least one bottom wiring layer from among the bottom and top wiring layers.

Abstract: A memory device includes an open-for-contact region located between the memory blocks, and a row decoder disposed between global lines to which an operating voltage is supplied and the local lines and configured to transfer the operating voltage to one memory block among the memory blocks in response to a row address, wherein a plurality of contacts are formed in the open-for-contact region and configured to transmit a voltage between the bit lines and a peripheral circuit, wherein a dummy region is included in the row decoder and disposed paced apart from the open-for-contact region in the second direction, and wherein a discharge switch is included in the dummy region and configured to discharge the global lines in response to a discharge signal.

Abstract: A memory device includes an open-for-contact region located between the memory blocks, and a row decoder disposed between global lines to which an operating voltage is supplied and the local lines and configured to transfer the operating voltage to one memory block among the memory blocks in response to a row address, wherein a plurality of contacts are formed in the open-for-contact region and configured to transmit a voltage between the bit lines and a peripheral circuit, wherein a dummy region is included in the row decoder and disposed paced apart from the open-for-contact region in the second direction, and wherein a discharge switch is included in the dummy region and configured to discharge the global lines in response to a discharge signal.

Abstract: A memory device includes a substrate defined with a first cell region and a second cell region, and a row decoder region between the first and second cell regions; a peripheral circuit defined in the first and second cell regions of the substrate; pass transistors defined in the row decoder region of the substrate; bottom wiring layers disposed in a first dielectric layer covering the peripheral circuit and the pass transistors; a memory cell array defined on the first dielectric layer; a second dielectric layer defined on the first dielectric layer, and covering the memory cell array; top wiring layers disposed in a third dielectric layer defined on the second dielectric layer; and global lines disposed in the row decoder region, and configured to transfer operating voltages to the pass transistors, wherein the global lines are disposed only in at least one bottom wiring layer from among the bottom and top wiring layers.

Abstract: A semiconductor memory device includes a substrate having a second region extending in a first direction; a memory block including electrodes; a slit dividing the memory block into first and second electrode structures in the second region; and step-shaped grooves formed in the memory block in the second region, and divided by the slit. In the second region, the first and second electrode structures are adjacently disposed with the slit interposed therebetween, in a second direction intersecting with the first direction. Each of the electrodes of the first electrode structure has a first pad region, each of the electrodes of the second electrode structure has a second pad region, and first and second pad regions of the first and second electrode structures which are positioned in the same step-shaped groove and are disposed at the same layers are adjacently disposed in the second direction with the slit interposed therebetween.

Abstract: A semiconductor memory device includes a substrate having a second region extending in a first direction; a memory block including electrodes; a slit dividing the memory block into first and second electrode structures in the second region; and step-shaped grooves formed in the memory block in the second region, and divided by the slit. In the second region, the first and second electrode structures are adjacently disposed with the slit interposed therebetween, in a second direction intersecting with the first direction. Each of the electrodes of the first electrode structure has a first pad region, each of the electrodes of the second electrode structure has a second pad region, and first and second pad regions of the first and second electrode structures which are positioned in the same step-shaped groove and are disposed at the same layers are adjacently disposed in the second direction with the slit interposed therebetween.

Abstract: The present invention relates to a two-stage fuel injection valve. The two-stage fuel injection valve of the present invention is configured such that the pressure of main fuel delivered from an injection pump is applied to a plunger in a main fuel chamber, and subsequently delivered to an ancillary fuel pressure chamber via the plunger so as to compress ancillary fuel, such that a needle is retracted in a manner similar to those of slide valves by means of the pressure of the ancillary fuel so as to open an ancillary fuel nozzle hole and inject the ancillary fuel, and a main fuel nozzle hole is opened after the injection of the ancillary fuel so as to inject the main fuel, thereby conducting two-stage fuel injection.

Abstract: The present invention relates to a two-stage fuel injection valve. The two-stage fuel injection valve of the present invention is configured such that the pressure of main fuel delivered from an injection pump is applied to a plunger in a main fuel chamber, and subsequently delivered to an ancillary fuel pressure chamber via the plunger so as to compress ancillary fuel, such that a needle is retracted in a manner similar to those of slide valves by means of the pressure of the ancillary fuel so as to open an ancillary fuel nozzle hole and inject the ancillary fuel, and a main fuel nozzle hole is opened after the injection of the ancillary fuel so as to inject the main fuel, thereby conducting two-stage fuel injection.