Abstract: A multi-bit capacitorless DRAM according to the embodiment of the present invention may be provided that includes: a substrate; a source and a drain formed on the substrate; a plurality of nanowire channels formed on the substrate; a gate insulation layer formed in the plurality of nanowire channels; and a gate formed on the gate insulation layer. Two or more nanowire channels among the plurality of nanowire channels have different threshold voltages. Each of the nanowire channels includes: a silicon layer; a first epitaxial layer which is formed to surround the silicon layer; and a second epitaxial layer which is formed to surround the first epitaxial layer. As a result, the high integration multi-bit capacitorless DRAM which operates at multi-bits can be implemented and a performance of accumulating excess holes can be improved by using energy band gap.

Abstract: A multi-bit capacitorless DRAM according to the embodiment of the present invention may be provided that includes: a substrate; a source and a drain formed on the substrate; a plurality of nanowire channels formed on the substrate; a gate insulation layer formed in the plurality of nanowire channels; and a gate formed on the gate insulation layer. Two or more nanowire channels among the plurality of nanowire channels have different threshold voltages. Each of the nanowire channels includes: a silicon layer; a first epitaxial layer which is formed to surround the silicon layer; and a second epitaxial layer which is formed to surround the first epitaxial layer. As a result, the high integration multi-bit capacitorless DRAM which operates at multi-bits can be implemented and a performance of accumulating excess holes can be improved by using energy band gap.

Abstract: An apparatus for cooling a vehicle engine includes a combustion chamber having a reciprocating piston, a water jacket for flowing cooling water to cool the combustion chamber, and a cylinder block forming a structure of the engine, wherein the cylinder block is equipped with a cylinder block body that includes the combustion chamber, and wherein the cylinder block includes a plurality of EGR coolers that exchange heat with the cooling water supplied to the combustion chamber.

Abstract: A power transmission apparatus for a vehicle may include a first input shaft selectively connected to an output side of an internal combustion engine through a first clutch, a second input shaft disposed at the first input shaft without any rotational interference and selectively connected to the output side of the internal combustion engine through a second clutch, a motor/generator performing a function of a motor and a generator, and a planetary gear set including first, second, and third rotation elements such that the first rotation element is directly connected with the motor/generator, the second rotation element is selectively connected with the second input shaft so as to be in synchronization with each other, and the third rotation element is directly connected with the first input shaft.

Abstract: Provided is a multi-pulsed jets generating apparatus including: at least one actuator that generates pulsed jets in a plurality of orifices according to a volume change of a plurality of cavities caused by vibration of at least one diaphragm; and a manifold connected to the at least one actuator so as to generate multi-pulsed jets by receiving the pulsed jets occurring in the plurality of orifices. The velocity and uniformity of the pulsed jets occurring in the plurality of injection ports can be controlled according to vibration phases of a plurality of diaphragms.

Abstract: An FFS mode LCD device is disclosed which includes: a substrate; gate and data lines arranged to cross each other on the substrate and define white, red, green and blue sub-pixels with asymmetric areas; first through fourth thin film transistors connected to the white, red, green and blue sub-pixels; common electrodes disposed in the white, red, green and blue sub-pixels; and white, red, green and blue pixel electrodes disposed to overlap with the common electrodes within the white, red, green and blue sub-pixels.

Abstract: A power transmission apparatus for a vehicle may include a first input shaft selectively connected to an output side of an internal combustion engine through a first clutch, a second input shaft disposed at the first input shaft without any rotational interference and selectively connected to the output side of the internal combustion engine through a second clutch, a motor/generator performing a function of a motor and a generator, and a planetary gear set including first, second, and third rotation elements such that the first rotation element is directly connected with the motor/generator, the second rotation element is selectively connected with the second input shaft so as to be in synchronization with each other, and the third rotation element is directly connected with the first input shaft.

Abstract: A display panel according to an embodiment includes a plurality of gate lines and a plurality of data lines disposed to cross each other and define a plurality of sub-pixel regions; and a plurality of sub-pixels disposed in the plurality of sub-pixel regions and configured to share one of the data lines adjacent thereto. The sub-pixels sharing the same data line are arranged in a shape of zigzagging along a vertical direction by four sub-pixels.

Abstract: The present disclosure relates to a liquid crystal display device and a fabricating method thereof. The liquid crystal display device includes: first and second substrates bonded to each other; gate lines aligned on the first substrate; a data line and a common line on the first substrate; a large pixel electrode disposed at the intersecting point between the lines; a TFT at the intersecting point between the gate line and the data line; a protrusion pattern on the gate line; a passivation layer on the first substrate; branched common electrodes on the passivation layer; a pixel electrode connection pattern on the passivation layer; a black matrix and color filter layer on the second substrate; a column spacer on the second substrate; and a liquid crystal layer at between the substrates.

Abstract: A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.

Abstract: An array substrate for a narrow bezel type liquid crystal display device and method of manufacturing the same are provided. The array substrate includes: gate lines (GLs) on a substrate, the substrate including a display area and first to fourth non-display areas at respective sides, pixel regions, a gate insulating layer (GIL) on the GLs, a plurality of data lines on the GIL and crossing the GLs, a plurality of gate auxiliary lines parallel to the data lines and connected to respective GLs, an auxiliary line in the third non-display area with a first layer under the GIL and a second layer on the GIL, the first layer contacting the second layer through a first auxiliary contact hole in the GIL, a thin film transistor in each pixel region and connected to the GLs and data lines, and a pixel electrode connected to each thin film transistor.

Abstract: An array substrate for a field switching mode liquid crystal display device and a fabrication method thereof are provided. The array substrate for an FFS mode LCD device includes: a plurality of gate lines formed on the substrate; a plurality of data lines arranged to cross the gate lines; a common line formed at the subpixel regions of the substrate; an auxiliary common line formed on the common line; TFTs formed at crossings of the gate lines and the data lines; a protective film formed on the substrate; and a pixel electrode and a common electrode formed on the protective film and connected with the TFTs and the auxiliary common line, respectively.

Abstract: A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.

Abstract: A method for operating a memory device is disclosed. The method includes receiving a serial data and a serial cyclic redundancy check (CRC) code transmitted sequentially through a channel, converting the serial data into a parallel data and the serial CRC code into a parallel CRC code, outputting the parallel data at a first time point, outputting the parallel CRC code at a second time point later than the first time point, calculating a CRC code by using the parallel data, comparing the parallel CRC code and the calculated CRC code with each other and detecting an error of the serial data transmitted through the channel according to the result of the comparison, and outputting an error detection signal in response to the result of the comparison.

Abstract: A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.

Abstract: An array substrate for a narrow bezel type liquid crystal display device and method of manufacturing the same are provided. The array substrate includes: gate lines (GLs) on a substrate, the substrate including a display area and first to fourth non-display areas at respective sides, pixel regions, a gate insulating layer (GIL) on the GLs, a plurality of data lines on the GIL and crossing the GLs, a plurality of gate auxiliary lines parallel to the data lines and connected to respective GLs, an auxiliary line in the third non-display area with a first layer under the GIL and a second layer on the GIL, the first layer contacting the second layer through a first auxiliary contact hole in the GIL, a thin film transistor in each pixel region and connected to the GLs and data lines, and a pixel electrode connected to each thin film transistor.

Abstract: A semiconductor package including a first connection terminal group configured to receive a first signal group from the outside of the semiconductor package, a second connection terminal group configured to transmit a second signal group to the outside, a first chip connected to the first connection terminal group, and a second chip connected to the second connection terminal group and configured to receive the first and second signal groups from the first chip. Degradation of the performance of the semiconductor package, caused by the differences between signal delay times in a plurality of chips therein may be minimized.

Abstract: The present disclosure relates to a liquid crystal display device and a fabricating method thereof. The liquid crystal display device includes: first and second substrates bonded to each other; gate lines aligned on the first substrate; a data line and a common line on the first substrate; a large pixel electrode at the intersecting point between the lines; a TFT at the intersecting point between the gate line and the data line; a protrusion pattern on the gate line; a passivation layer on the first substrate; branched common electrodes on the passivation layer; a pixel electrode connection pattern on the passivation layer; a black matrix and color filter layer on the second substrate; a column spacer on the second substrate; and a liquid crystal layer at between the substrates.

Abstract: A method for operating a memory device is disclosed. The method includes receiving a serial data and a serial cyclic redundancy check (CRC) code transmitted sequentially through a channel, converting the serial data into a parallel data and the serial CRC code into a parallel CRC code, outputting the parallel data at a first time point, outputting the parallel CRC code at a second time point later than the first time point, calculating a CRC code by using the parallel data, comparing the parallel CRC code and the calculated CRC code with each other and detecting an error of the serial data transmitted through the channel according to the result of the comparison, and outputting an error detection signal in response to the result of the comparison.

Abstract: Provided are a photoreactive polymer that includes a multi-cyclicmulticyclic compound at as its main chain and a method of preparing the same. The photoreactive polymer exhibits excellent thermal stability since it includes a multi-cyclicmulticyclic compound having a high glass transition temperature at as its main chain. In addition, the photoreactive polymer has a relatively large vacancy so that a photoreactive group can move relatively freely in the main chain therein. As a result, a slow photoreaction rate, which is a disadvantage of a conventional polymer material used to form an alignment layer for a liquid crystal display device, can be overcome.