Patents by Inventor Byung-Jick CHO
Byung-Jick CHO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11950522Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.Type: GrantFiled: June 22, 2022Date of Patent: April 2, 2024Assignee: SK hynix Inc.Inventors: Myoung Sub Kim, Tae Hoon Kim, Beom Seok Lee, Seung Yun Lee, Hwan Jun Zang, Byung Jick Cho, Ji Sun Han
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Patent number: 11882775Abstract: An electronic device comprises a semiconductor memory that includes: a first line; a second line disposed over the first line to be spaced apart from the first line; a variable resistance layer disposed between the first line and the second line; a first electrode layer disposed between the first line and the variable resistance layer; and a first oxide layer disposed between the variable resistance layer and the first electrode layer. The first electrode layer includes a first carbon material doped with a first element, and the first oxide layer includes a first oxide of the first element.Type: GrantFiled: September 3, 2021Date of Patent: January 23, 2024Assignee: SK hynix Inc.Inventors: Ji Sun Han, Yong Hun Sung, Byung Jick Cho
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Patent number: 11864476Abstract: An electronic device comprises a semiconductor memory that includes: a first line; a second line disposed over the first line to be spaced apart from the first line; a variable resistance layer disposed between the first line and the second line; a selection element layer disposed between the first line and the variable resistance layer or between the second line and the variable resistance layer; and one or more electrode layers disposed over or under the selection element layer or disposed over and under the selection element layer, the one or more electrode layers being adjacent to the selection element layer, wherein each of the one or more electrode layers includes a first electrode layer and a second electrode layer, the second electrode layer including a second carbon layer containing nitrogen, the first electrode layer including a first carbon layer containing a lower concentration of nitrogen or containing no nitrogen.Type: GrantFiled: July 7, 2021Date of Patent: January 2, 2024Assignee: SK hynix Inc.Inventors: Byung Jick Cho, Yong Hun Sung, Ji Sun Han
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Publication number: 20220328762Abstract: An electronic device comprises a semiconductor memory that includes: a first line; a second line disposed over the first line to be spaced apart from the first line; a variable resistance layer disposed between the first line and the second line; a first electrode layer disposed between the first line and the variable resistance layer; and a first oxide layer disposed between the variable resistance layer and the first electrode layer. The first electrode layer includes a first carbon material doped with a first element, and the first oxide layer includes a first oxide of the first element.Type: ApplicationFiled: September 3, 2021Publication date: October 13, 2022Inventors: Ji Sun HAN, Yong Hun SUNG, Byung Jick CHO
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Publication number: 20220320427Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.Type: ApplicationFiled: June 22, 2022Publication date: October 6, 2022Inventors: Myoung Sub KIM, Tae Hoon KIM, Beom Seok LEE, Seung Yun LEE, Hwan Jun ZANG, Byung Jick CHO, Ji Sun HAN
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Publication number: 20220310916Abstract: An electronic device comprises a semiconductor memory that includes: a first line; a second line disposed over the first line to be spaced apart from the first line; a variable resistance layer disposed between the first line and the second line; a selection element layer disposed between the first line and the variable resistance layer or between the second line and the variable resistance layer; and one or more electrode layers disposed over or under the selection element layer or disposed over and under the selection element layer, the one or more electrode layers being adjacent to the selection element layer, wherein each of the one or more electrode layers includes a first electrode layer and a second electrode layer, the second electrode layer including a second carbon layer containing nitrogen, the first electrode layer including a first carbon layer containing a lower concentration of nitrogen or containing no nitrogen.Type: ApplicationFiled: July 7, 2021Publication date: September 29, 2022Inventors: Byung Jick CHO, Yong Hun SUNG, Ji Sun HAN
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Patent number: 11430952Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.Type: GrantFiled: August 4, 2020Date of Patent: August 30, 2022Assignee: SK hynix Inc.Inventors: Myoung Sub Kim, Tae Hoon Kim, Beom Seok Lee, Seung Yun Lee, Hwan Jun Zang, Byung Jick Cho, Ji Sun Han
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Publication number: 20210280781Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.Type: ApplicationFiled: August 4, 2020Publication date: September 9, 2021Inventors: Myoung Sub KIM, Tae Hoon KIM, Beom Seok LEE, Seung Yun LEE, Hwan Jun ZANG, Byung Jick CHO, Ji Sun HAN
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Patent number: 9520186Abstract: A semiconductor memory may include: a first stacked structure including a first word line disposed over a substrate and extended in a first direction, a first bit line disposed over the first word line and extended in a second direction crossing the first direction, and a first variable resistance layer interposed between the first word line and the first bit line; and a second stacked structure including a second bit line disposed over the first stacked structure and extended in the second direction, a second word line disposed over the second bit line and extended in the first direction, and a second variable resistance layer interposed between the second word line and the second bit line; and a first selecting element layer interposed between the first bit line and the second bit line.Type: GrantFiled: February 7, 2014Date of Patent: December 13, 2016Assignee: SK HYNIX INC.Inventors: Hyo-June Kim, Ja-Chun Ku, Sung-Kyu Min, Seung-Beom Baek, Byung-Jick Cho, Won-Ki Ju, Hyun-Kyu Kim, Jong-Chul Lee
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Patent number: 9418008Abstract: An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction intersecting the first direction, and a plurality of variable resistance patterns that is positioned at intersections of the first lines and the second lines and disposed between the first lines and the second lines in a vertical direction. Each of the variable resistance patterns has an elongated shape in a plan view and a portion of each of the variable resistance patterns is disposed outside a region in which a corresponding first line and a corresponding second line overlap with each other.Type: GrantFiled: October 24, 2014Date of Patent: August 16, 2016Assignee: SK HYNIX INC.Inventors: Kyoo-Ho Jung, Byung-Jick Cho, Jong-Chul Lee, Won-Ki Ju
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Publication number: 20160005462Abstract: An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction intersecting the first direction, and a plurality of variable resistance patterns that is positioned at intersections of the first lines and the second lines and disposed between the first lines and the second lines in a vertical direction. Each of the variable resistance patterns has an elongated shape in a plan view and a portion of each of the variable resistance patterns is disposed outside a region in which a corresponding first line and a corresponding second line overlap with each other.Type: ApplicationFiled: October 24, 2014Publication date: January 7, 2016Inventors: Kyoo-Ho JUNG, Byung-Jick CHO, Jong-Chul LEE, Won-Ki JU
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Patent number: 9105840Abstract: According to embodiments, a semiconductor memory may include: a variable resistance pattern disposed over a substrate and extended in a first direction; first and second structures including a plurality of interlayer dielectric layers and a plurality of conductive layers which are alternately stacked over the substrate, and contacted with one side surface and the other side surface of the variable resistance pattern, respectively, wherein the first stacked structure has a line shape extended in a first direction and the second stacked structure has a pillar shape; and a pillar-shaped conductive pattern contacted with one side surface of the second stacked structure, which is not contacted with the variable resistance pattern.Type: GrantFiled: March 6, 2014Date of Patent: August 11, 2015Assignee: SK HYNIX INC.Inventors: Jong-Chul Lee, Ja-Chun Ku, Sung-Kyu Min, Byung-Jick Cho, Seung-Beom Baek, Hyo-June Kim, Won-Ki Ju, Hyun-Kyu Kim
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Publication number: 20150085559Abstract: According to embodiments, a semiconductor memory may include: a variable resistance pattern disposed over a substrate and extended in a first direction; first and second structures including a plurality of interlayer dielectric layers and a plurality of conductive layers which are alternately stacked over the substrate, and contacted with one side surface and the other side surface of the variable resistance pattern, respectively, wherein the first stacked structure has a line shape extended in a first direction and the second stacked structure has a pillar shape; and a pillar-shaped conductive pattern contacted with one side surface of the second stacked structure, which is not contacted with the variable resistance pattern.Type: ApplicationFiled: March 6, 2014Publication date: March 26, 2015Applicant: SK HYNIX INC.Inventors: Jong-Chul LEE, Ja-Chun KU, Sung-Kyu MIN, Byung-Jick CHO, Seung-Beom BAEK, Hyo-June KIM, Won-Ki JU, Hyun-Kyu KIM
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Publication number: 20150089087Abstract: A semiconductor memory may include: a first stacked structure including a first word line disposed over a substrate and extended in a first direction, a first bit line disposed over the first word line and extended in a second direction crossing the first direction, and a first variable resistance layer interposed between the first word line and the first bit line; and a second stacked structure including a second bit line disposed over the first stacked structure and extended in the second direction, a second word line disposed over the second bit line and extended in the first direction, and a second variable resistance layer interposed between the second word line and the second bit line; and a first selecting element layer interposed between the first bit line and the second bit line.Type: ApplicationFiled: February 7, 2014Publication date: March 26, 2015Applicant: SK HYNIX INC.Inventors: Hyo-June KIM, Ja-Chun KU, Sung-Kyu MIN, Seung-Beom BAEK, Byung-Jick CHO, Won-Ki JU, Hyun-Kyu KIM, Jong-Chul LEE