Abstract: A capacitor component includes a body, including a dielectric layer and an internal electrode layer, and an external electrode disposed on the body and connected to the internal electrode layer. At least one hole is formed in the internal electrode layer, and a region, containing at least one selected from the group consisting of indium (In) and tin (Sn), is disposed in the hole. A method of manufacturing a capacitor component includes forming a dielectric green sheet, forming a conductive thin film, including a first conductive material and a second conductive material, on the dielectric green sheet, and sintering the conductive thin film to form an internal electrode layer. The internal electrode layer includes the first conductive material, and a region, including the second conductive material, is formed in the internal electrode layer.

Abstract: A high-sensitive contactless chromaticity measuring device according to the present invention, includes: a lens unit to receive light emitted from a measurement object; a light distribution unit including an optical fiber to receive the light passing through the lens unit and distribute the received light through n paths to output the light to the other side, wherein a numerical aperture is greater than a predetermined reference value, a condensing lens to reduce an incidence angle of the light output to the other side of the optical fiber to a target angle or more, and n color filters to transmit different wavelengths of the light passing through the condensing lens; and a signal conversion unit including a photodiode to convert the light transmitted from the light distribution unit into an electrical signal.

Abstract: Disclosed is a color and luminance measuring device including a filter unit including a case which covers the entire device and has a light incident part formed on one side thereof through which measured light emitted from an object to be measured is incident, a measurement unit which measures luminance and a color by receiving the measured light in the case, and a filter unit which is disposed on a movement path of the measured light in the case to selectively control the luminance of the measured light transmitted to the measurement unit and transmit the measured light, wherein the filter unit reduces the luminance of the measured light to a predetermined level when the measured light has luminance of a predetermined level or higher and transmits the measured light to the measurement unit.

Abstract: Disclosed is a color and luminance measuring device including a filter unit including a case which covers the entire device and has a light incident part formed on one side thereof through which measured light emitted from an object to be measured is incident, a measurement unit which measures luminance and a color by receiving the measured light in the case, and a filter unit which is disposed on a movement path of the measured light in the case to selectively control the luminance of the measured light transmitted to the measurement unit and transmit the measured light, wherein the filter unit reduces the luminance of the measured light to a predetermined level when the measured light has luminance of a predetermined level or higher and transmits the measured light to the measurement unit.

Abstract: A color measuring device includes a color difference meter module. The color difference meter module includes: a main detecting unit having an optical detecting unit configured to receive light introduced from an incident lens to generate a first current depending on a color, a first measuring unit configured to measure the first current, a sub-detecting unit having a dark detecting unit disposed adjacent to the main detecting unit and blocking the light to generate a second current in a dark state, a second measuring unit configured to measure the second current, a leakage measuring unit including a charging unit provided in the second measuring unit and charged with a predetermined set current, and measures a third current leaking from the charging unit, and a control unit that corrects the first current by reflecting the second current and the third current.

Abstract: A color measuring device includes a color difference meter module. The color difference meter module includes: a main detecting unit having an optical detecting unit configured to receive light introduced from an incident lens to generate a first current depending on a color, a first measuring unit configured to measure the first current, a sub-detecting unit having a dark detecting unit disposed adjacent to the main detecting unit and blocking the light to generate a second current in a dark state, a second measuring unit configured to measure the second current, a leakage measuring unit including a charging unit provided in the second measuring unit and charged with a predetermined set current, and measures a third current leaking from the charging unit, and a control unit that corrects the first current by reflecting the second current and the third current.

Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer.

Abstract: A capacitor may include a first electrode, a second electrode, a low dielectric layer, and/or a high dielectric layer. The first electrode may include at least one first electrode branch. The second electrode may face the first electrode and include at least one second electrode branch. The low dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may have a higher dielectric constant than the low dielectric layer.

Abstract: In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

Abstract: A capacitor may include a first electrode, a second electrode, a low dielectric layer, and/or a high dielectric layer. The first electrode may include at least one first electrode branch. The second electrode may face the first electrode and include at least one second electrode branch. The low dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may have a higher dielectric constant than the low dielectric layer.

Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer.

Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer.

Abstract: A method of forming metal wiring in a semiconductor device is disclosed. The method uses a dual damascene process in which a trench is formed prior to a via-hole.

Abstract: In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer.

Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a Metal-Insulator-Metal (MIM) capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the MIM capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer.

Abstract: A method of forming metal wiring in a semiconductor device is disclosed. The method uses a dual damascene process in which a trench is formed prior to a via-hole.

Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a Metal-Insulator-Metal (MIM) capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the MIM capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer.