Patents by Inventor Byung-kwon CHO

Byung-kwon CHO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11887868
    Abstract: A substrate processing apparatus includes a vessel providing a processing space for processing a substrate, a substrate support supporting the substrate loaded in the processing space, and a barrier between a side wall of the vessel and the substrate support and surrounding an edge of the substrate supported by the substrate support.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: January 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-hoo Kim, Sang-jine Park, Yong-jhin Cho, Yeon-jin Gil, Ji-hoon Jeong, Byung-kwon Cho, Yong-sun Ko, Kun-tack Lee
  • Patent number: 11302526
    Abstract: A supercritical drying apparatus and a method of drying a substrate, the apparatus including a drying chamber configured to receive a supercritical fluid and to dry a substrate; a chuck in the drying chamber, the chuck being configured to receive the substrate; and a particle remover in the drying chamber, the particle remover being configured to remove dry particles from the substrate by heating the substrate with radiant heat.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 12, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangjine Park, Byung-Kwon Cho, Jihoon Jeong, Youngtak Kim, Yongsun Ko, Seulgee Jeon
  • Publication number: 20210217635
    Abstract: A substrate processing apparatus includes a vessel providing a processing space for processing a substrate, a substrate support supporting the substrate loaded in the processing space, and a barrier between a side wall of the vessel and the substrate support and surrounding an edge of the substrate supported by the substrate support.
    Type: Application
    Filed: March 29, 2021
    Publication date: July 15, 2021
    Inventors: Young-hoo Kim, Sang-jine PARK, Yong-jhin CHO, Yeon-jin GIL, Ji-hoon JEONG, Byung-kwon CHO, Yong-sun KO, Kun-tack LEE
  • Patent number: 10985036
    Abstract: A substrate processing apparatus includes a vessel providing a processing space for processing a substrate, a substrate support supporting the substrate loaded in the processing space, and a barrier between a side wall of the vessel and the substrate support and surrounding an edge of the substrate supported by the substrate support.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 20, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Hoo Kim, Sang-Jine Park, Yong-Jhin Cho, Yeon-Jin Gil, Ji-Hoon Jeong, Byung-Kwon Cho, Yong-Sun Ko, Kun-Tack Lee
  • Patent number: 10818522
    Abstract: Disclosed are a supercritical process chamber and an apparatus having the same. The process chamber includes a body frame having a protrusion protruding in an upward vertical direction from a first surface of the body frame and a recess defined by the protrusion and the first surface of the body frame; a cover frame; a buffer chamber arranged between the body frame and the cover frame; and a connector. The buffer chamber includes an inner vessel detachably coupled to the body frame providing a chamber space in the recess and an inner cover detachably coupled to the cover frame. The inner cover is in contact with a first surface of the inner vessel enclosing the chamber space from surroundings. The connector couples the body frame and the cover frame having the buffer chamber arranged therebetween such that the enclosed chamber space is transformed into a process space in which the supercritical process is performed.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Jine Park, Byung-Kwon Cho, Yong-Jhin Cho, Yong-Sun Ko, Yeon-Jin Gil, Kwang-Wook Lee
  • Publication number: 20200227253
    Abstract: A supercritical drying apparatus and a method of drying a substrate, the apparatus including a drying chamber configured to receive a supercritical fluid and to dry a substrate; a chuck in the drying chamber, the chuck being configured to receive the substrate; and a particle remover in the drying chamber, the particle remover being configured to remove dry particles from the substrate by heating the substrate with radiant heat.
    Type: Application
    Filed: September 5, 2019
    Publication date: July 16, 2020
    Inventors: Sangjine PARK, Byung-Kwon CHO, Jihoon JEONG, Youngtak KIM, Yongsun KO, Seulgee JEON
  • Publication number: 20190096712
    Abstract: Disclosed are a supercritical process chamber and an apparatus having the same. The process chamber includes a body frame having a protrusion protruding in an upward vertical direction from a first surface of the body frame and a recess defined by the protrusion and the first surface of the body frame; a cover frame; a buffer chamber arranged between the body frame and the cover frame; and a connector. The buffer chamber includes an inner vessel detachably coupled to the body frame providing a chamber space in the recess and an inner cover detachably coupled to the cover frame. The inner cover is in contact with a first surface of the inner vessel enclosing the chamber space from surroundings. The connector couples the body frame and the cover frame having the buffer chamber arranged therebetween such that the enclosed chamber space is transformed into a process space in which the supercritical process is performed.
    Type: Application
    Filed: May 14, 2018
    Publication date: March 28, 2019
    Inventors: Sang-Jine PARK, Byung-Kwon CHO, Yong-Jhin CHO, Yong-Sun KO, Yeon-Jin GIL, Kwang-Wook LEE
  • Patent number: 10192973
    Abstract: A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: January 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Bo-Un Yoon, Ha-Young Jeon, Byung-Kwon Cho, Jeong-Nam Han
  • Patent number: 10186485
    Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: January 22, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: VietHa Nguyen, Wookyung You, Inoue Naoya, Hak-Sun Lee, Byung-Kwon Cho, Songyi Han, Jongmin Baek, Jiwon Kang, Byunghee Kim, Young-Ju Park, Sanghoon Ahn, Jiwon Yun, Naein Lee, YoungWoo Cho
  • Publication number: 20180358242
    Abstract: A substrate processing apparatus includes a vessel providing a processing space for processing a substrate, a substrate support supporting the substrate loaded in the processing space, and a barrier between a side wall of the vessel and the substrate support and surrounding an edge of the substrate supported by the substrate support.
    Type: Application
    Filed: November 30, 2017
    Publication date: December 13, 2018
    Inventors: Young-hoo Kim, Sang-jine PARK, Yong-jhin CHO, Yeon-jin GIL, Ji-hoon JEONG, Byung-kwon CHO, Yong-sun KO, Kun-tack LEE
  • Publication number: 20180174977
    Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.
    Type: Application
    Filed: February 15, 2018
    Publication date: June 21, 2018
    Inventors: VietHa Nguyen, Wookyung You, Inoue Naoya, Hak-Sun Lee, Byung-Kwon Cho, Songyi Han, Jongmin Baek, Jiwon Kang, Byunghee Kim, Young-Ju Park, Sanghoon Ahn, Jiwon Yun, Naein Lee, YoungWoo Cho
  • Patent number: 9984921
    Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: May 29, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Hoon Ahn, Jong Min Baek, Myung Geun Song, Woo Kyung You, Byung Kwon Cho, Byung Hee Kim, Na Ein Lee
  • Patent number: 9929099
    Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: March 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: VietHa Nguyen, Wookyung You, Inoue Naoya, Hak-Sun Lee, Byung-Kwon Cho, Songyi Han, Jongmin Baek, Jiwon Kang, Byunghee Kim, Young-Ju Park, Sanghoon Ahn, Jiwon Yun, Naein Lee, YoungWoo Cho
  • Publication number: 20180053685
    Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.
    Type: Application
    Filed: November 3, 2017
    Publication date: February 22, 2018
    Inventors: Sang Hoon AHN, Jong Min BAEK, Myung Geun SONG, Woo Kyung YOU, Byung Kwon CHO, Byung Hee KIM, Na Ein LEE
  • Patent number: 9812353
    Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Hoon Ahn, Jong Min Baek, Myung Geun Song, Woo Kyung You, Byung Kwon Cho, Byung Hee Kim, Na Ein Lee
  • Publication number: 20170170184
    Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.
    Type: Application
    Filed: November 21, 2016
    Publication date: June 15, 2017
    Inventors: VietHa Nguyen, Wookyung You, Inoue Naoya, Hak-Sun Lee, Byung-Kwon Cho, Songyi Han, Jongmin Baek, Jiwon Kang, Byunghee Kim, Young-Ju Park, Sanghoon Ahn, Jiwon Yun, Naein Lee, YoungWoo Cho
  • Publication number: 20170162431
    Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.
    Type: Application
    Filed: November 17, 2016
    Publication date: June 8, 2017
    Inventors: Sang Hoon AHN, Jong Min BAEK, Myung Geun SONG, Woo Kyung YOU, Byung Kwon CHO, Byung Hee KIM, Na Ein LEE
  • Publication number: 20160359017
    Abstract: A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.
    Type: Application
    Filed: August 17, 2016
    Publication date: December 8, 2016
    Inventors: Sang-Jine PARK, Bo-Un YOON, Ha-Young JEON, Byung-Kwon CHO, Jeong-Nam HAN
  • Publication number: 20160318684
    Abstract: The present invention relates to a pouch container including a pouch main body to be filled with liquid contents; an inner tube which includes an inserted portion to be inserted in the pouch main body, an inlet portion for putting or withdrawing the liquid contents in or out, and a connecting portion of connecting the inserted portion and the inlet portion, and provides a tubular passage for the liquid contents; and an outer tube which is softer than the inner tube, and surrounds at least one of the connecting portion and the inlet portion. Thus, it is possible to solve problems of inconvenience and prevents damage to a consumer when s/he drinks liquid contents since the inlet portion is partially made of a soft material.
    Type: Application
    Filed: December 19, 2013
    Publication date: November 3, 2016
    Inventors: Byung-chul Jo, Byoung-gu Cho, Byung-kwon Cho
  • Patent number: 9443979
    Abstract: A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: September 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Bo-Un Yoon, Ha-Young Jeon, Byung-Kwon Cho, Jeong-Nam Han