Abstract: Various techniques are disclosed to identify composite wires from segmented wires of a programmable logic device (PLD). In one example, a method includes associating segmented wires of the PLD with a plurality of wire index values based on connections identified by interface templates. The method further includes identifying a plurality of composite wires according to the wire index values. Each composite wire comprises a set of the segmented wires associated with a corresponding one of the wire index values. The composite wires are adapted to interconnect programmable logic blocks of the PLD.

Abstract: A computer-implemented method of referencing wires of a routing graph of a programmable logic device (PLD). In one embodiment, the method includes mapping the first routing graph wire to a master wire; mapping the first master wire to master switch; identifying a segmented wire connected to the master switch; mapping the identified segmented wire to a second master wire; and mapping the second master wire to the second routing graph wire.

Abstract: Various techniques for referencing components of a programmable logic device (PLD) are provided. In one example, a method of referencing wires of a routing graph of a PLD is provided. The routing graph comprises a plurality of routing graph wires and a plurality of routing graph switches corresponding to components of the PLD. The method includes maintaining a plurality of master tiles comprising a plurality of master wires and a plurality of master switches corresponding to the routing graph wires and the routing graph switches, respectively. The method also includes identifying a first one of the routing graph wires. The method further includes mapping the first routing graph wire to a second one of the routing graph wires using at least one of the master wires.

Abstract: Various techniques are described to identify composite wires from segmented wires of a programmable logic device (PLD). In one example, a method includes identifying a plurality of interface templates corresponding to tiles of the PLD. The PLD comprises a plurality of segmented wires arranged in a plurality of tiles. Each interface template corresponds to at least two adjacent tiles of the PLD and identifies connections between segmented wires of the corresponding adjacent tiles. The method also includes associating the segmented wires of the PLD with a plurality of wire index values based on the connections identified by the interface templates. The method further includes identifying a plurality of composite wires according to the wire index values. Each composite wire comprises a set of the segmented wires associated with a corresponding one of the wire index values. The composite wires are adapted to interconnect programmable logic blocks of the PLD.