Abstract: A positive electrode active material for a secondary battery includes a lithium composite transition metal oxide including nickel (Ni), cobalt (Co), and manganese (Mn), wherein the lithium composite transition metal oxide has a layered crystal structure of space group R3m, includes the nickel (Ni) in an amount of 60 mol % or less based on a total amount of transition metals, includes the cobalt (Co) in an amount greater than an amount of the manganese (Mn), and is composed of single particles.

Abstract: A wafer manufacturing method, an epitaxial wafer manufacturing method, and a wafer and epitaxial wafer manufactured thereby, are provided. The wafer manufacturing method enables the manufacture of a wafer with a low density of micropipe defects and minimum numbers of particles and scratches. The epitaxial wafer manufacturing method enables the manufacture of an epitaxial wafer that has low densities of defects such as downfall, triangular, and carrot defects, exhibits excellent device characteristics, and improves the yield of devices.

Abstract: A wafer manufacturing method, an epitaxial wafer manufacturing method, and a wafer and epitaxial wafer manufactured thereby, are provided. The wafer manufacturing method enables the manufacture of a wafer with a low density of micropipe defects and minimum numbers of particles and scratches. The epitaxial wafer manufacturing method enables the manufacture of an epitaxial wafer that has low densities of defects such as downfall, triangular, and carrot defects, exhibits excellent device characteristics, and improves the yield of devices.

Abstract: A cylindrical secondary battery and a manufacturing method of a secondary battery are provided. A manufacturing method of a cylindrical secondary battery includes: winding an electrode assembly to expose a first electrode uncoated portion and a second electrode uncoated portion to opposite ends in a longitudinal direction; bending at least some portions of the first electrode uncoated portion and the second electrode uncoated portion of the electrode assembly in a direction by pressing the first electrode uncoated portion and the second electrode uncoated portion; welding electrode collector plates to ends of the bent first and second electrode uncoated portions; and inserting and sealing the electrode assembly into a cylindrical case.

Abstract: A display device includes: a first substrate including first, second, and third light emitting areas, first, second, and third pixel electrodes respectively in the first, second, and third light emitting areas on the first substrate, a pixel defining layer in the non-light emitting area on the first substrate and defining a peripheral opening partially overlapping the non-light emitting area, a second substrate including first, second, and third light transmitting areas and a light blocking area surrounding the first, second, and third light transmitting areas, a bank layer in the light blocking area on one surface of the second substrate, defining a first opening overlapping each of the first, second, and third light transmitting areas, and defining second openings overlapping the light blocking area wherein each of the second openings has a polygonal planar shape, and a color conversion layer in the first opening and including color conversion particles.

Abstract: A display device includes: a plurality of light emitting elements; an encapsulation layer disposed on the light emitting elements to cover the light emitting elements; a foreign substance disposed on at least one of the light emitting elements, where the foreign substance is disposed through at least a portion of the encapsulation layer and a protruding part is defined by a portion protruding from a top flat surface of the encapsulation layer by the foreign substance; a reinforcing filling layer disposed on the encapsulation layer to cover the protruding part; a filling layer disposed on the encapsulation layer and the reinforcing filling layer; and a color conversion layer disposed on the filling layer.

Abstract: Test structures and alignment marks enable accurate measurements of alignment in the active area of an image sensor device. The alignment marks are formed in the active area replacing pixels near the lithographic shot boundaries of the array. Misalignment across the lithographic shots is assessed through the degree of shifting between the alignment patterns. The alignment marks are located in a pixel location of the active area and can measure the actual lithographic shot-to-shot misalignment in the active area, which can be used to make an accurate lithographic alignment. Having such alignment marks allows for a more accurate assessment of the in-line process manufacturing capability as well as a more rapid feedback of in-array drift, which would allow a faster and better control for yield loss.

Abstract: An image sensor array includes pixels arranged in rows and columns, wherein each pixel includes a transistor serially coupled to a photodiode, data lines coupled to a first node of the pixel, bias lines coupled to a second node of the pixel, gate lines coupled to a third node of the pixel, and electrostatic-discharge (ESD) circuits coupled between the gate lines and an ESD bus, wherein the ESD circuits each include first and second metal oxide offset bottom gate transistors in parallel connection.

Abstract: The present invention relates to a radiation-resistant metal oxide semiconductor composition containing zinc-indium-tin oxide (ZITO) exhibiting radiation resistance, and a preparation method and use thereof. In the present invention, the radiation-resistant metal oxide semiconductor composition containing ZITO exhibiting radiation resistance is used in an electronic device for radiation exposure, which is used in outer space, nuclear power plants, or in spaces where medical or security devices are utilized by means of radiation, and thus, the damage caused by radiation can be prevented, thereby improving the electrical properties of the device (e.g., turn-on voltage (Von)), and the life-span and reliability thereof.

Abstract: An image sensor array includes pixels arranged in rows and columns, wherein each pixel includes a transistor serially coupled to a photodiode, data lines coupled to a first node of the pixel, bias lines coupled to a second node of the pixel, gate lines coupled to a third node of the pixel, and electrostatic-discharge (ESD) circuits coupled between the gate lines and an ESD bus, wherein the ESD circuits each include first and second metal oxide offset bottom gate transistors in parallel connection.

Abstract: An ESD circuit includes a first metal oxide channel device having a drain coupled to a first node, a source coupled to a second node, and a gate coupled to the first node; a second metal oxide channel device having a source coupled to the first node, a drain coupled to the second node, and a gate coupled to the second node; a first capacitor coupled between the first and second nodes proximate to the first metal oxide channel device; and a second capacitor coupled between the first and second nodes proximate to the second metal oxide channel device. The ESD circuit can further include a third capacitor coupled between the first and second nodes proximate to the first capacitor. The ESD circuit can further include a fourth capacitor coupled between the first and second nodes proximate to the second capacitor.

Abstract: A test structure for characterizing an organic photodiode image sensor includes, on a common substrate, a cathode sheet resistance portion; a diode capacitance portion; an organic photodiode sheet resistance portion; a contact resistance portion; a step coverage portion; a quantum efficiency portion; a film adhesion portion; and an inkjet printing portion. The organic photodiode sheet resistance portion includes gate metal sets, each gate metal set including four evenly spaced metal lines terminating in a probe point, wherein the spacing within each gate metal set is progressively increased from a first gate metal set to a last gate metal set, and wherein a spacing between each gate metal set is larger than the spacing within any gate metal set; and an organic photodiode sheet formed over the gate metal sets.

Abstract: A method of manufacturing a sensor array includes providing a carrier glass substrate, forming an amorphous silicon layer over the carrier glass substrate, forming a first heat buffer layer over the amorphous silicon layer; forming a mirror layer over the first heat buffer layer; forming a second heat buffer layer over the mirror layer; forming a flexible substrate over the second heat buffer layer; and forming an active device layer over the flexible substrate. The method of the present invention further comprises exposing the sensor array to light from a flash lamp and then detaching the carrier glass substrate from the sensor array. The method of the present invention optionally further comprises filtering the light from the flash lamp to wavelengths below 350 nm.

Abstract: Test structures and alignment marks enable accurate measurements of alignment in the active area of an image sensor device. The alignment marks are formed in the active area replacing pixels near the lithographic shot boundaries of the array. Misalignment across the lithographic shots is assessed through the degree of shifting between the alignment patterns. The alignment marks are located in a pixel location of the active area and can measure the actual lithographic shot-to-shot misalignment in the active area, which can be used to make an accurate lithographic alignment. Having such alignment marks allows for a more accurate assessment of the in-line process manufacturing capability as well as a more rapid feedback of in-array drift, which would allow a faster and better control for yield loss.

Abstract: An ESD circuit includes a first metal oxide channel device having a drain coupled to a first node, a source coupled to a second node, and a gate coupled to the first node; a second metal oxide channel device having a source coupled to the first node, a drain coupled to the second node, and a gate coupled to the second node; a first capacitor coupled between the first and second nodes proximate to the first metal oxide channel device; and a second capacitor coupled between the first and second nodes proximate to the second metal oxide channel device. The ESD circuit can further include a third capacitor coupled between the first and second nodes proximate to the first capacitor. The ESD circuit can further include a fourth capacitor coupled between the first and second nodes proximate to the second capacitor.