Abstract: In a method and apparatus for polishing a Cu metal layer and a method for forming Cu metal wiring, Cu oxide created by a surface oxidation of a Cu metal layer is removed from the wafer. The Cu metal layer, in which Cu oxide is removed, is polished. By polishing the Cu metal layer using the above method, process failures, such as scratches, caused by the presence of remnants of Cu oxide during subsequent polishing can be prevented.

Abstract: In a method and apparatus for polishing a Cu metal layer and a method for forming Cu metal wiring, Cu oxide created by a surface oxidation of a Cu metal layer is removed from the wafer. The Cu metal layer, in which Cu oxide is removed, is polished. By polishing the Cu metal layer using the above method, process failures, such as scratches, caused by the presence of remnants of Cu oxide during subsequent polishing can be prevented.

Abstract: A contact structure includes a lower conductive pattern disposed on a predetermined region of a semiconductor substrate. The lower conductive layer has a concave region at a predetermined region of a top surface thereof. An embedding conductive layer fills the concave region. The top surface of the embedding conductive layer is placed at least as high as the height of the flat top surface of the lower conductive pattern. A mold layer is disposed to cover the semiconductor substrate, the lower conductive pattern and the embedding conductive layer. An upper conductive pattern is arranged in an intaglio pattern. The intaglio pattern is disposed in the mold layer to expose a predetermined region of the embedding conductive layer.

Abstract: A method for manufacturing a semiconductor device having a metal-insulator-metal (MIM) capacitor and a damascene wiring layer structure, wherein first and second metal wiring layers are formed in a lower dielectric layer on a semiconductor substrate such that top surfaces of the first and second metal wiring layers and the lower dielectric layer are level. First and second dielectric layers are sequentially formed to have a hole exposing the top surface of the second metal wiring layer. An upper electrode of a capacitor is formed in the hole region such that the top surfaces of the upper electrode and the second dielectric layer are level. Third and fourth dielectric layers are sequentially formed on the substrate. A damascene structure is formed to contact the top surface of the first metal wiring layer, and a contact plug is formed to contact the top surface of the upper electrode.

Abstract: In a method and apparatus for polishing a Cu metal layer and a method for forming Cu metal wiring, Cu oxide created by a surface oxidation of a Cu metal layer is removed from the wafer. The Cu metal layer, in which Cu oxide is removed, is polished. By polishing the Cu metal layer using the above method, process failures, such as scratches, caused by the presence of remnants of Cu oxide during subsequent polishing can be prevented.

Abstract: A method for manufacturing a semiconductor device having a metal-insulator-metal (MIM) capacitor and a damascene wiring layer structure, wherein first and second metal wiring layers are formed in a lower dielectric layer on a semiconductor substrate such that top surfaces of the first and second metal wiring layers and the lower dielectric layer are level. First and second dielectric layers are sequentially formed to have a hole exposing the top surface of the second metal wiring layer. An upper electrode of a capacitor is formed in the hole region such that the top surfaces of the upper electrode and the second dielectric layer are level. Third and fourth dielectric layers are sequentially formed on the substrate. A damascene structure is formed to contact the top surface of the first metal wiring layer, and a contact plug is formed to contact the top surface of the upper electrode.

Abstract: A semiconductor device having a capacitor. The capacitor includes a first electrode, a dielectric layer formed of a metal oxide layer including a Ta2O5 layer, and a second electrode composed of first and second metal nitride layers sequentially stacked. Each of the first and second metal nitride layers has a TiN layer and a WN layer. The second electrode of the capacitor is a double-layered structure having the first and second metal nitride layers, and thus annealing after forming the second electrode is performed at 750° C. or less, to thereby reduce an equivalent oxide thickness of the dielectric layer.

Abstract: A semiconductor device having a capacitor. The capacitor includes a first electrode, a dielectric layer formed of a metal oxide layer including a Ta2O5 layer, and a second electrode composed of first and second metal nitride layers sequentially stacked. Each of the first and second metal nitride layers has a TiN layer and a WN layer. The second electrode of the capacitor is a double-layered structure having the first and second metal nitride layers, and thus annealing after forming the second electrode is performed at 750° C. or less, to thereby reduce an equivalent oxide thickness of the dielectric layer.

Abstract: The capacitor of semiconductor devices includes a first electrode, a dielectric layer formed of a metal oxide layer including a Ta2O5 layer, and a second electrode composed of first and second metal nitride layers sequentially stacked. First and second metal nitride layers are a TiN layer and a WN layer. The second electrode of the capacitor is a double-layered structure having the first and second metal nitride layers, and thus annealing after forming the second electrode is performed at 750° C. or less to avoid increasing an equivalent oxide thickness of the dielectric layer.

Abstract: A tungsten or other metal layer is chemical vapor deposited using a source gas containing tungsten, a reducing gas and a nitrogen-containing gas. The nitrogen-containing gas can act as a surface roughness reducing gas that reduces the roughness of the tungsten layer compared to a tungsten layer that is chemical vapor deposited using the source gas containing tungsten and the reducing gas, but without using the surface roughness reducing gas. Viewed in another way, the nitrogen-containing gas acts as a growth rate controlling gas that produces uniform growth of the tungsten layer in a plurality of directions compared to a tungsten layer that is deposited using the source gas containing tungsten and the reducing gas, but without using the growth rate controlling gas.

Abstract: Methods for fabricating a tungsten nitride layer in a semiconductor substrate having an insulating layer formed thereon. The methods include forming a contact hole through the insulating layer. A tungsten nitride layer is then selectively deposited only in the contact hole by selectively reacting a nitrogen-containing gas with a tungsten source gas so as to prevent formation of tungsten nitride layer on the insulating layer outside the contact hole. Methods or fabricating metal wiring utilizing the methods of fabricating a tungsten nitride layer are also provided.

Abstract: A method of manufacturing a metal wiring layer in a semiconductor device, wherein an insulating layer is plasma treated before a tungsten nitride film is formed on the insulating layer. A metal, metal silicide or metal alloy thereafter being deposited over the tungsten nitride film.

Abstract: A method of manufacturing a semiconductor capacitor electrode by growing a metal compound layer over polysilicon storage nodes. The metal compound layer readily growing on the polysilicon storage nodes, but not on portions of an insulating layer between adjacent polysilicon storage nodes.

Abstract: A frit-drying system for cathode ray tubes is to utilize VHF and it is to evaporate organic matters which are contained in the frit spread on the funnel by a VHF dielectric heating method that matters with dipole components are heated from the inner part of the frit by dielectric loss of VHF when the VHF is injected on the matters with dipole components. A frit-drying system for cathode ray tubes utilizing VHF includes a funnel transferring device, and a main furnace body which defines the VHF room for drying frit therein, a VHF oscillating device, and VHF induction path which inducts VHF generated from the VHF oscillating device into the main furnace body.

Abstract: There is provided a method for manufacturing a capacitor in a semiconductor device including the steps of forming first and second insulating layers with a first contact hole through to a semiconductor substrate, patterning a first conductive layer to form a pedestal portion of a lower electrode, using a patterned third insulating layer selectively forming an upper portion of the lower electrode from a tungsten nitride thin film, and forming an undercut beneath the pedestal portion by wet-etching the second insulating layer.