Abstract: A coil component includes a body having a first surface, and a first end surface and a second end surface connected to the first surface and opposing each other in a length direction; a support substrate disposed inside the body; a coil portion comprising a first coil pattern and first and second lead-out patterns, each disposed on a first surface of the support substrate; first and second slit portions, respectively defined on edge portions of the first surface of the body to expose the first and second lead-out patterns; and first and second external electrodes disposed on the first and second slit portions to be connected to the first and second lead-out patterns. At least one of the first and second lead-out patterns has a thickness greater than a thickness of each of the first coil pattern and the first dummy lead-out pattern.

Abstract: A coil component is provided. The coil component includes a body having fifth and sixth surfaces opposing each other, first and second surfaces respectively connecting the fifth and sixth surfaces of the body and opposing each other, and third and fourth surfaces respectively connecting the first and second surfaces of the body and opposing each other in one direction, a recess disposed in an edge between one of the first and second surfaces of the body and the sixth surface of the body, a coil portion disposed inside the body and exposed through the recess, and an external electrode including a connection portion disposed in the recess and connected to the coil portion, and a pad portion disposed on one surface of the body. A length of the pad portion in the one direction is greater than a length of the connection portion in the one direction.

Abstract: Rambus Dynamic Random Access Memory (DRAM) devices may have their functional blocks arranged effectively in an integrated circuit substrate. A first memory core block an interface logic block, a pad block, an input/output and internal clock signal generation block, a data shift block and a second memory core block are sequentially arranged in one axial direction of the substrate. Accordingly, the lengths of data lines for transmitting data between a data input/output unit of the input/output and internal clock signal generation block and the data shift block may be reduced so that loads on the data lines may be reduced, thereby allowing data transmission speed to be maintained and/or power consumption to be reduced. Moreover, the data lines need not be wired between pads in the pad block, which can prevent the width of the substrate from increasing.