Abstract: A circuit to translate virtual addresses of varied page sizes into physical addresses enables selective access to an internally stored data in parallel to reading a specific physical address based on the input virtual address before the internally stored data matches in entirety for the address translation thereof. In one embodiment, a content addressed buffer may comprise at least two register files or static random access memories. For example, a banked architecture for a set associative translation lookaside buffer may reduce power consumption without compromising address translation speed.

Abstract: Techniques and apparatuses for reducing power consumption in processor based systems during active and standby modes. A low power TLB is disclosed that does not precharge invalid entries or write to output circuits physical addresses that are the same as immediately preceding lookups. A circuit to acknowledge that the integrated circuits of the processor have entered low power standby mode that is low leakage and consumes little power is disclosed. Minimum delay buffers that have very low leakage because of series placement of a long delay enable transistor with the transistors of the inverters that make up the buffers is also disclosed.