Abstract: Provided is a three-dimensional storage device using wafer-to-wafer bonding. A storage device includes a first chip including a first substrate and a peripheral circuit region including a first control logic circuit configured to control operation modes of the non-volatile memory device and a second chip including a second substrate and three-dimensional arrays of non-volatile memory cells. The second chip may be vertically stacked on the first chip so that a first surface of the first substrate faces a first surface of the second substrate, and a second control logic circuit is configured to control operation conditions of the non-volatile memory device and is arranged on a second surface of the second substrate, the second surface of the second substrate being opposite to the first surface of the second substrate of the second chip.

Abstract: A nonvolatile memory (NVM) device includes a plurality of memory blocks and a control logic receiving a specific command and an address. The control logic may perform a cell count-based dynamic read (CDR) operation on memory cells connected to one of wordlines of a selected block, among the plurality of memory blocks, in response to the address. The control logic includes a cell count comparator circuit configured to compare: (1) a first cell count value for a highest state among a plurality of states with at least one reference value according to the CDR operation and (2) a second cell count value for an erase state among the plurality of states with the at least one reference value. Additionally, the control logic includes a read level selector configured to select a read level according to a result of the comparison of the cell count comparator circuit.

Abstract: Provided is a semiconductor device. The semiconductor device includes: a plurality of insulating layers and a plurality of gate electrodes alternately arranged in a first direction; and a plurality of channel structures passing through the plurality of gate electrodes and the plurality of insulating layers in the first direction, wherein each of the plurality of gate electrodes includes: a first conductive layer including an inner wall surrounding the plurality of channel structures; and a second conductive layer that is separated from the plurality of channel structures in a second direction perpendicular to the first direction, wherein resistivity of the second conductive layer is less than resistivity of the first conductive layer.

Abstract: An apparatus includes a transistor coupled between an input pin and an output pin and an overvoltage detection circuit configured to receive a serial interface signal from the input pin and generate an enable signal in response to a voltage of the serial interface signal exceeding a voltage threshold. The apparatus also includes a first circuit configured to apply a clamping voltage to a gate of the transistor based on the enable signal to regulate a voltage provided at the output pin.

Abstract: Frequency lock loop (FLL) circuits, low voltage dropout regulator circuits, and related methods are disclosed. An example gate driver integrated circuit includes a first die including a FLL circuit to generate a first clock signal having a first phase and a first frequency, a second clock signal having the first frequency and a second phase different from the first phase, and control a plurality of switching networks to increase the first frequency to a second frequency, and generate a feedback voltage based on the second frequency, and a second die coupled to the first die, the second die including a low dropout (LDO) circuit and a driver, the driver configured to control a transistor based on the first frequency, the second die configured to be coupled to the transistor, the LDO circuit to generate a pass-gate voltage based on an output current of the LDO circuit satisfying a current threshold.

Abstract: Frequency lock loop (FLL) circuits, low voltage dropout regulator circuits, and related methods are disclosed. An example gate driver integrated circuit includes a first die including a FLL circuit to generate a first clock signal having a first phase and a first frequency, a second clock signal having the first frequency and a second phase different from the first phase, and control a plurality of switching networks to increase the first frequency to a second frequency, and generate a feedback voltage based on the second frequency, and a second die coupled to the first die, the second die including a low dropout (LDO) circuit and a driver, the driver configured to control a transistor based on the first frequency, the second die configured to be coupled to the transistor, the LDO circuit to generate a pass-gate voltage based on an output current of the LDO circuit satisfying a current threshold.

Abstract: An apparatus includes a transistor coupled between an input pin and an output pin and an overvoltage detection circuit configured to receive a serial interface signal from the input pin and generate an enable signal in response to a voltage of the serial interface signal exceeding a voltage threshold. The apparatus also includes a first circuit configured to apply a clamping voltage to a gate of the transistor based on the enable signal to regulate a voltage provided at the output pin.

Abstract: USB controllers, systems and methods are presented to conserve power in a USB controller, in which a transmitter transmits data to a line of a connected USB cable according to a transmit data signal, and a pull down circuit selectively sinks current from a supply node of the transmitter when the transmit data signal is in a first state, refrains from sinking the first current from the supply node when the transmit data signal is in a different second state.

Abstract: A Charge Pump Buck Converter (CPBC) includes a BC including an inductor and a CP coupled in parallel. Control logic is coupled to a switch driver coupled to a power switch(es). Control circuitry includes a voltage sensor sensing Vout and a voltage level generator for generating a first voltage level coupled to the CP stage and a second voltage level coupled to a duty cycle/rate generator block providing an input to an under voltage (UV) monitor coupled between OUT and the control logic. The control circuitry disables the CP when Vout>a first Vout level and controls the BC to regulate to a second Vout level>the first Vout level. During handoff between CP and BC during power up if Vout drops below a UV threshold, the UV monitor block modifies an input applied to the control logic for increasing charging supplied to the inductor.

Abstract: A switch-mode DC-DC voltage converter including a boost stage in the form of a charge pump and a buck stage. Control circuitry is provided that enables the operation of the buck stage while the charge pump stage is also enabled, followed by disabling of the charge pump stage as the input voltage and output voltage increase. The buck converter stage is constructed so that it regulates the output voltage at a voltage above that which disables the charge pump stage. Conduction losses in the main current path, due to the necessity of a power FET or other switching device, are avoided.

Abstract: USB controllers, systems and methods are presented to conserve power in a USB controller, in which a transmitter transmits data to a line of a connected USB cable according to a transmit data signal, and a pull down circuit selectively sinks current from a supply node of the transmitter when the transmit data signal is in a first state, refrains from sinking the first current from the supply node when the transmit data signal is in a different second state.

Abstract: A Charge Pump Buck Converter (CPBC) includes a BC including an inductor and a CP coupled in parallel. Control logic is coupled to a switch driver coupled to a power switch(es). Control circuitry includes a voltage sensor sensing Vout and a voltage level generator for generating a first voltage level coupled to the CP stage and a second voltage level coupled to a duty cycle/rate generator block providing an input to an under voltage (UV) monitor coupled between OUT and the control logic. The control circuitry disables the CP when Vout>a first Vout level and controls the BC to regulate to a second Vout level>the first Vout level. During handoff between CP and BC during power up if Vout drops below a UV threshold, the UV monitor block modifies an input applied to the control logic for increasing charging supplied to the inductor.

Abstract: A switch-mode DC-DC voltage converter including a boost stage in the form of a charge pump and a buck stage. Control circuitry is provided that enables the operation of the buck stage while the charge pump stage is also enabled, followed by disabling of the charge pump stage as the input voltage and output voltage increase. The buck converter stage is constructed so that it regulates the output voltage at a voltage above that which disables the charge pump stage. Conduction losses in the main current path, due to the necessity of a power FET or other switching device, are avoided.

Abstract: A biosensor system incorporating CMOS integrated circuits. In one type of biosensor system, the biosensor system includes a silicon substrate. The biosensor system further includes active devices fabricated on the silicon substrate. Additionally, the biosensor system includes a plurality of metal layers stacked on top of the active devices. Furthermore, the biosensor system includes a passivation layer covering a top metal layer, where the passivation layer includes an opening configured to expose the top metal layer, where the opening is used as a sensing electrode. Additionally, the biosensor system includes a plurality of probes attached to the sensing electrode.

Abstract: Traditionally, charge pumps, which used flying capacitors, were limited to a maximum divide ratio of N+1 (where N is the number of flying capacitors). Here, however, a charge pump has been provided that allows for a dramatically increased divide ratio. Specifically, several switched capacitor circuits (which are controlled by a driver) allow for flying capacitors to be arranged to provide a maximum divide ratio of 3·2(N-1)?1.

Abstract: The present invention discloses a process for preparing catalyst solution for a membrane-electrode assembly in a fuel cell, which comprises the steps of a) mixing a catalyst solution (Solution A) wherein catalyst particles are dispersed in water and an ion conductive resin solution (Solution B) wherein an ion conductive resin is dissolved in water, low boiling point organic solvent or a mixture thereof, to form a dispersion; b) mixing the dispersion obtained from step a) with functional additive dissolved in high boiling point solvent or a mixture of low boiling point solvent arid water (Solution C) to prepare catalyst ink dispersion; and c) aging the catalyst ink dispersion obtained from step b).

Abstract: Traditionally, charge pumps, which used flying capacitors, were limited to a maximum divide ratio of N+1 (where N is the number of flying capacitors). Here, however, a charge pump has been provided that allows for a dramatically increased divide ratio. Specifically, several switched capacitor circuits (which are controlled by a driver) allow for flying capacitors to be arranged to provide a maximum divide ratio of 3·2(N-1)?1.

Abstract: A biosensor system incorporating CMOS integrated circuits. In one type of biosensor system, the biosensor system includes a silicon substrate. The biosensor system further includes active devices fabricated on the silicon substrate. Additionally, the biosensor system includes a plurality of metal layers stacked on top of the active devices. Furthermore, the biosensor system includes a passivation layer covering a top metal layer, where the passivation layer includes an opening configured to expose the top metal layer, where the opening is used as a sensing electrode. Additionally, the biosensor system includes a plurality of probes attached to the sensing electrode.

Abstract: The present invention relates to a process for the preparation of electrochemical catalysts of the polymer electrolytes-based fuel cells. With the process of the present invention, high catalyst activity while uniformly supporting a large amount of metal particles on a surface of a support can be achieved. Also, the present invention provides a process for the preparation of electrochemical catalysts of the polymer electrolytes-based fuel cells capable of using a small amount of toxic solvent without an additional high-temperature hydrogen annealing.

Abstract: The present invention discloses a process for preparing catalyst solution for a membrane-electrode assembly in a fuel cell, which comprises the steps of a) mixing a catalyst solution (Solution A) wherein catalyst particles are dispersed in water and an ion conductive resin solution (Solution B) wherein an ion conductive resin is dissolved in water, low boiling point organic solvent or a mixture thereof, to form a dispersion; b) mixing the dispersion obtained from step a) with functional additive dissolved in high boiling point solvent or a mixture of low boiling point solvent arid water (Solution C) to prepare catalyst ink dispersion; and c) aging the catalyst ink dispersion obtained from step b).