Abstract: Provided are a GIP driving circuit and a display device using the same. The GIP driving circuit includes: a plurality of stages which sequentially receives a phase-delayed clock and sequentially generates an output. An nth stage (n is a positive integer) includes: a first switch T1 receiving a carry signal from an n?1th stage and controlling a QB node to a low voltage and a Q node to a high voltage when the carry signal has a high voltage; a second switch T2 receiving a carry signal from an n+1th stage and controlling the QB and Q nodes high and low voltages, respectively, when the carry signal has a high voltage; a plurality of inverters connected between nodes Q and QB and constituting a latch; and a buffer outputting a clock as an output voltage when a voltage of the Q node is a high voltage and output.

Abstract: Provided are a gate driving circuit and a display device using the same. The gate driving circuit includes: a plurality of stages, each stage sequentially receiving a phase-delayed clock and sequentially generating an output. An nth stage (n is a positive integer) includes: a first inverter including a first PMOS transistor and a first NMOS transistor; a second inverter including a second PMOS transistor and a second NMOS transistor; and a reset signal line connected to a source terminal of the second NMOS transistor and supplying a reset signal to initiate the nth stage.

Abstract: Provided are a gate driving circuit and a display device including the same. The gate driving circuit according to an embodiment includes a shift register including a plurality of stages. An nth stage of the stages includes a latch control circuit including a first NMOS transistor connected to a QB node, a second NMOS transistor connected to a Q node, and a third NMOS transistor having a gate electrode to which a first clock is input and connected to the first and second NMOS transistors, where n is a positive integer. A latch is connected between the Q and QB nodes. A transmission gate is connected to the Q and QB nodes. In the gate driving circuit, output signals of a previous stage and a following stage are controlled so as to be synchronized with the first clock to suppress a glitch.

Abstract: Provided are a gate driving circuit and a display device using the same, and the gate driving circuit includes a shift register which includes stages. The n-th stage (n is a positive integer) includes an auto reset circuit that receive a first clock and a carry signal received from an (n?1)-th stage, regulates a Q node to be at a low voltage when the first clock is at a high voltage and the carry signal is at a low voltage, and regulates the Q node to be at a high voltage when both of the first clock and the carry signal are at a high voltage.

Abstract: The present invention relates to; a pharmaceutical compostion capable of enhancing immunity against viruses by specifically decreasing the expression of the OASL1 protein; and a method for screening for a material capable of being used as an antiviral agent by comparing the amount of expression of the OASL1 protein.