Abstract: A feed forward equalizer includes a plurality of delay circuits connected to each other in series and configured to delay input signals. A plurality of filters respectively correspond to outputs of the plurality of delay circuits, except for a reference output which is an output of a first delay circuit among the plurality of delay circuits, and the input signals. A calculator configured to sum the reference output and outputs of the plurality of filters. Each of the plurality of filters is configured to receive an output of a delay circuit corresponding thereto, among the plurality of filters, and the reference output.

Abstract: A data transmitter includes a transmitting circuit configured to transmit data, the data including alternating odd-numbered data and even-numbered data. The transmitting circuit includes a first flip flop configured to receive the odd-numbered data and generate retimed odd-numbered data, and a second flip flop configured to receive the even-numbered data and generate retimed even-numbered data. The data transmitter includes a clock transmitting circuit configured to supply a clock signal to the transmitting circuit, the clock transmitting circuit including a clock driver configured to transmit the clock signal to a receiver that receives the data.

Abstract: A system for transceiving data based on a clock transition time is provided. A transmitting device included in the system includes at least one first transmitting circuit configured to transmit data via a wired channel by changing a clock transition time based on the data, wherein the at least one first transmitting circuit includes a skew controller configured to output a skew clock generated by controlling a duty ratio and a skew of an input clock, and a phase-difference modulator configured to output a transmission signal including information about the data generated by changing a transition time of the skew clock based on the data.

Abstract: Provided are a transmitting device connected to a receiving device via a channel and the receiving device connected to the transmitting device via a channel. The transmitting device connected to a receiving device includes: a transmitter connected to the channel via an output node and configured to transmit, via the channel, a transmission signal to the receiving device, the transmitter having a transmission impedance associated therewith that is variable; and a monitoring device configured to detect a channel impedance of the channel and a receiving impedance of the receiving device by monitoring a voltage level of the output node, the monitoring device configured to set the transmission impedance based on the channel impedance and the receiving impedance.

Abstract: Provided are a transmitting device connected to a receiving device via a channel and the receiving device connected to the transmitting device via a channel. The transmitting device connected to a receiving device includes: a transmitter connected to the channel via an output node and configured to transmit, via the channel, a transmission signal to the receiving device, the transmitter having a transmission impedance associated therewith that is variable; and a monitoring device configured to detect a channel impedance of the channel and a receiving impedance of the receiving device by monitoring a voltage level of the output node, the monitoring device configured to set the transmission impedance based on the channel impedance and the receiving impedance.

Abstract: A system for transceiving data based on a clock transition time is provided. A transmitting device included in the system includes at least one first transmitting circuit configured to transmit data via a wired channel by changing a clock transition time based on the data, wherein the at least one first transmitting circuit includes a skew controller configured to output a skew clock generated by controlling a duty ratio and a skew of an input clock, and a phase-difference modulator configured to output a transmission signal including information about the data generated by changing a transition time of the skew clock based on the data.

Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.

Abstract: The present invention relates to a coefficient error robust feed forward equalizer and, more specifically, to a feed forward equalizing transmitter for baseband wired communication for preventing the influence of a coefficient error generated by the variation of nano-elements. The coefficient error robust feed forward equalizer according to one embodiment of the present invention comprises: a receiving terminal (130) for receiving input data (x) according to an integer time index (n), N number of delay units (D) connected with the input terminal (130) in series, a first calculator (110) for summing up tap signals outputted respectively from the N number of delay units (D); and a data change detection filter (120) for outputting a data transition value (b) on the basis of the change in the input data (x).

Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a separate summer circuit configured to add a respective feedback signal to a received input and a latch configured to receive an output of the summer circuit to provide different partial bit sequences based on a clock signal. A feedback circuit includes a multiplexer configured to multiplex the different partial bit sequences of each branch to assemble a full rate bit sequence and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input.

Abstract: The present invention relates to a coefficient error robust feed forward equalizer and, more specifically, to a feed forward equalizing transmitter for baseband wired communication for preventing the influence of a coefficient error generated by the variation of nano-elements. The coefficient error robust feed forward equalizer according to one embodiment of the present invention comprises: a receiving terminal (130) for receiving input data (x) according to an integer time index (n), N number of delay units (D) connected with the input terminal (130) in series, a first calculator (110) for summing up tap signals outputted respectively from the N number of delay units (D); and a data change detection filter (120) for outputting a data transition value (b) on the basis of the change in the input data (x).

Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.

Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a separate summer circuit configured to add a respective feedback signal to a received input and a latch configured to receive an output of the summer circuit to provide different partial bit sequences based on a clock signal. A feedback circuit includes a multiplexer configured to multiplex the different partial bit sequences of each branch to assemble a full rate bit sequence and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input.

Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.

Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.

Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.

Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.

Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.