Abstract: A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. P-type base regions of the TLPM and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.

Abstract: A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. P-type base regions of the TLPM and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.

Abstract: A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. P-type base regions of the TLPM and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.

Abstract: The phase shifted (PS) transmitter provides substantially linear amplification from two non-linear amplifiers by decomposing the original signal into two constant envelope signals with varying phases. The generation of the two constant envelope signals does not require the use of a signal component separator (SCS) or a reference signal generator. The phase shifted transmitter generates directly the required constant envelope, varying phase signals. This eliminates stringent requirements on the circuitry and allows the use of non-linear highly efficient power amplifiers in the transmitter. When the two above mentioned signals are combined, they constructively and destructively interfere to re-form an amplified form of the original signal, which is to be transmitted via an antenna.

Abstract: A lateral double diffused MOSFET (LDMOST) incorporates both the reduced surface field (RESURF) and super junction (SJ) in a split-drift region to significantly improve the on-state, off-state and switching characteristics in junction-isolated (JI) technology. The structure effectively suppresses substrate-assisted-depletion which is the main problem encountered when applying the SJ concept to lateral power devices. The device structure features a split-drift region formed of two parts: a SJ structure that extends over most of the drift region, and a terminating RESURF region occupying a portion of the drift region next to the drain. The structure offers improved breakdown voltage and reduced specific on resistance as compared to convention structures, and is useful in power integrated circuits suitable for a variety of applications including flat plasma panel display, automotive electronics, motor control, power supply and high voltage lamp ballasts.

Abstract: A trench-type lateral power MOSFET is manufactured by forming an n?-type diffusion region, which will be a drift region, on a p?-type substrate; selectively removing a part of substrate and a part of n?-type diffusion region to form trenches; forming a gate oxide film of 0.05 ?m in thickness in each trench; forming a polycrystalline silicon gate layer on gate oxide film; forming a p?-type base region and an n+-type diffusion region, which will be a source region, in the bottom of each trench; and forming an n+-type diffusion region, which will be a drain region, in the surface portion of n?-type diffusion region. The MOSFET has reduced device pitch, a reduced on-resistance per unit area and a simplified manufacturing process.

Abstract: A trench-type lateral power MOSFET is manufactured by forming an n−-type diffusion region, which will be a drift region, on a p−-type substrate; selectively removing a part of substrate and a part of n−-type diffusion region to form trenches; forming a gate oxide film of 0.05 &mgr;m in thickness in each trench; forming a polycrystalline silicon gate layer on gate oxide film; forming a p−-type base region and an n+-type diffusion region, which will be a source region, in the bottom of each trench; and forming an n+-type diffusion region, which will be a drain region, in the surface portion of n−-type diffusion region.

Abstract: A semiconductor integrated circuit (IC) device that integrates a TLPM and one or more planar semiconductor devices on a semiconductor substrate and a method of manufacturing the semiconductor IC device. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. PLPM type base regions of the TLPN and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.

Abstract: A trench-type lateral power MOSFET is manufactured by forming an n−-type diffusion region, which will be a drift region, on a p−-type substrate; selectively removing a part of substrate and a part of n−-type diffusion region to form trenches; forming a gate oxide film of 0.05 &mgr;m in thickness in each trench; forming a polycrystalline silicon gate layer on gate oxide film; forming a p−-type base region and an n+-type diffusion region, which will be a source region, in the bottom of each trench; and forming an n+-type diffusion region, which will be a drain region, in the surface portion of n30 -type diffusion region. The MOSFET has reduced device pitch, a reduced on-resistance per unit area and a simplified manufacturing process.

Abstract: A SJ-LDMOST device offers significantly improved on-state, off-state, and switching characteristics of lateral power devices for power integrated circuits applications. The device is fabricated on an insulator substrate. The proposed structure achieves charge compensation in the drift region by terminating the bottom of the SJ structure by a dielectric hence eliminating the undesirable vertical electric field component and preventing any substrate-assisted-depletion. The device structural arrangement thereby achieve a uniform distribution of the electric field thus maximizing the BV for a given drift region length.

Abstract: The phase shifted (PS) transmitter provides substantially linear amplification from two non-linear amplifiers by decomposing the original signal into two constant envelope signals with varying phases. The generation of the two constant envelope signals does not require the use of a signal component separator (SCS) or a reference signal generator. The phase shifted transmitter generates directly the required constant envelope, varying phase signals. This eliminates stringent requirements on the circuitry and allows the use of non-linear highly efficient power amplifiers in the transmitter. When the two above mentioned signals are combined, they constructively and destructively interfere to re-form an amplified form of the original signal, which is to be transmitted via an antenna.

Abstract: A semiconductor integrated circuit (IC) device that integrates a TLPM and one or more planar semiconductor devices on a semiconductor substrate and a method of manufacturing the semiconductor IC device. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. P-type base regions of the TLPM and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.

Abstract: A high-voltage and low on-resistance semiconductor device incorporates a trench structure that provides improved switching characteristics. In a preferred embodiment, a Trench Lateral Power MISFET is provided having a gate, channel and drift regions that are built on the side-walls of the trench. The process used to form the MISFET involves a self-aligned trench bottom contact hole to contact a source provided at the bottom of the trench to achieve minimum pitch and very low on-resistance. An example of a MISFET with 80 V breakdown voltage having a cell pitch of 3.4 microns is disclosed in which an on-resistance of 0.7 m&OHgr;-cm2 is realized. The switching characteristics of the MISFET are twice as good as that of prior MISFET device structures.

Abstract: A high-voltage and low on-resistance semiconductor device incorporates a trench structure that provides improved switching characteristics. In a preferred embodiment, a Trench Lateral Power MISFET is provided having a gate, channel and drift regions that are built on the side-walls of the trench. The process used to form the MISFET involves a self-aligned trench bottom contact hole to contact a source provided at the bottom of the trench to achieve minimum pitch and very low on-resistance. An example of a MISFET with 80 V breakdown voltage having a cell pitch of 3.4 microns is disclosed in which an on-resistance of 0.7 m&OHgr;-cm2 is realized. The switching characteristics of the MISFET are twice as good as that of prior MISFET device structures.

Abstract: A SJ-LDMOST device offers significantly improved on-state, off-state, and switching characteristics of lateral power devices for power integrated circuits applications. The device is fabricated on an insulator substrate. The proposed structure achieves charge compensation in the drift region by terminating the bottom of the SJ structure by a dielectric hence eliminating the undesirable vertical electric field component and preventing any substrate-assisted-depletion. The device structural arrangement thereby achieve a uniform distribution of the electric field thus maximizing the BV for a given drift region length.

Abstract: A trench-type lateral power MOSFET is manufactured by forming an n−-type diffusion region, which will be a drift region, on a p−-type substrate; selectively removing a part of substrate and a part of n−-type diffusion region to form trenches; forming a gate oxide film of 0.05 &mgr;m in thickness in each trench; forming a polycrystalline silicon gate layer on gate oxide film; forming a p−-type base region and an n+-type diffusion region, which will be a source region, in the bottom of each trench; and forming an n+-type diffusion region, which will be a drain region, in the surface portion of n−-type diffusion region.

Abstract: A high-voltage and low on-resistance semiconductor device incorporates a trench structure that provides improved switching characteristics. In a preferred embodiment, a Trench Lateral Power MISFET is provided having a gate, channel and drift regions that are built on the side-walls of the trench. The process used to form the MISFET involves a self-aligned trench bottom contact hole to contact a source provided at the bottom of the trench to achieve minimum pitch and very low on-resistance. An example of a MISFET with 80 V breakdown voltage having a cell pitch of 3.4 microns is disclosed in which an on-resistance of 0.7 m&OHgr;-cm2 is realized. The switching characteristics of the MISFET are twice as good as that of prior MISFET device structures.

Abstract: A high-voltage and low on-resistance semiconductor device incorporates a trench structure that provides improved switching characteristics. In a preferred embodiment, a Trench Lateral Power MISFET is provided having a gate, channel and drift regions that are built on the side-walls of the trench. The process used to form the MISFET involves a self-aligned trench bottom contact hole to contact a source provided at the bottom of the trench to achieve minimum pitch and very low on-resistance. An example of a MISFET with 80 V breakdown voltage having a cell pitch of 3.4 microns is disclosed in which an on-resistance of 0.7 m&OHgr;-cm2 is realized. The switching characteristics of the MISFET are twice as good as that of prior MISFET device structures.

Abstract: A semiconducting device and method of making the same are provided. The semiconducting device is provided with a gate, a source and a drain disposed on one side of a current carrying layer and a substrate formed from one type of semiconducting material disposed on the other side thereof. The current carrying layer includes a bulk region formed from said one type of semiconducting material and a drift region formed from the opposite type of semiconducting material, the bulk and the drift regions of which form a pn junction. The drift region includes a pair of parallel passages, one passage of which has a lower doping concentration than the other. The bulk region includes a first and a second portion, the first portion of which isolates the second portion from the other passage and has a lower doping concentration than the second portion and the one passage. The one passage is also extended so as to isolate the bulk region from the substrate.