Patents by Inventor C. C. Hsue
C. C. Hsue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6391760Abstract: A method of forming a local interconnect is provided. A semiconductor is provided. An isolation structure, a transistor and a conductive layer are formed on the substrate. A dielectric layer with an opening is formed over the substrate. A part of the dielectric layer is removed by a photolithography and etching process to form a via opening to expose a part of the gate of the transistor or a part of the conductive layer. A conformal barrier layer is formed in the via opening and overflows the dielectric layer. A conductive plug is formed in the via opening. The barrier layer is patterned to form a local interconnect.Type: GrantFiled: December 8, 1998Date of Patent: May 21, 2002Assignee: United Microelectronics Corp.Inventors: C. C. Hsue, Wei-Chung Chen
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Publication number: 20020004268Abstract: A method of polishing a polysilicon layer by using a chemical mechanical polishing process is described. A semiconductor substrate is provided, and a shallow trench isolation structure is formed on the semiconductor substrate such that the substrate has an uneven surface. A first polysilicon layer is formed on the semiconductor substrate and the shallow trench isolation structure. A polishing step is performed on the first polysilicon layer to planarize the first polysilicon layer. A second polysilicon layer is formed on the first polysilicon layer, wherein an interface is formed between the second polysilicon layer and the first polysilicon layer.Type: ApplicationFiled: February 8, 1999Publication date: January 10, 2002Inventors: TONY LIN, JIH-WEN CHOU, C.C. HSUE
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Patent number: 6313006Abstract: A method of field implantation. Using a photo-resist layer as a mask, a substrate is implanted with ions to forming a selectively distributed ion field.Type: GrantFiled: March 26, 1998Date of Patent: November 6, 2001Assignee: United Microelectronics, Corp.Inventors: C. C. Hsue, Sun-Chieh Chien
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Patent number: 6221710Abstract: A method of fabricating a capacitor on a semiconductor substrate. A barrier layer is formed over the substrate to serve as a bottom electrode of the capacitor. A dielectric layer is formed on the barrier layer. An upper electrode is formed on the dielectric layer. In addition, the method can be used in a dynamic random access memory.Type: GrantFiled: December 29, 1998Date of Patent: April 24, 2001Assignee: United Microelectronics Corp.Inventors: C. C. Hsue, Wei-Chung Chen
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Patent number: 6211027Abstract: A method for manufacturing a PMOS transistor. A gate terminal is formed over a substrate. Spacers are formed on the sidewalls of the gate terminal. A source/drain terminal is formed in the substrate on each side of the gate terminal, and then a metal silicide layer is formed over the top surface of the gate terminal and the substrate. The spacers are next removed. Using the metal silicide layer as a mask, a source/drain extension region is formed in the substrate between the gate terminal and the source/drain terminal. Similarly, using the metal silicide layer as a mask, an anti-punchthrough region is form in the substrate interior under the source/drain extension region.Type: GrantFiled: November 19, 1999Date of Patent: April 3, 2001Assignees: United Microelectronics Corp., United Silicon IncorporatedInventors: Tony Lin, C. C. Hsue
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Patent number: 6174791Abstract: A method for forming an amorphous silicon layer over the terminals of a MOS transistor. The method includes the steps of forming a mask layer having an opening that exposes the gate polysilicon layer over the MOS transistor. Next, using the mask layer as a mask, an inactive ion implant operation is carried out such that inactive ions are implanted into the gate polysilicon layer. Thereafter, again using the mask layer as a mask, a first heavy bombarding operation is carried out, implanting ions locally. Finally, the mask layer is removed and then a second heavy bombarding operation is carried out, implanting ions globally.Type: GrantFiled: March 25, 1999Date of Patent: January 16, 2001Assignee: United Microelectronics Corp.Inventors: Tony Lin, Jih-Wen Chou, C. C. Hsue
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Patent number: 6026012Abstract: A dual port random access memory (RAM). The dual port random access memory includes four N-MOS transistors and four P-MOS transistors. Both the N-MOS and the P-MOS transistors are used as pass gates. More specifically, two N-MOS transistors are used as pass gate for a set of bit lines and two P-MOS transistors are used as a pass gate to another set of bit lines.Type: GrantFiled: December 30, 1998Date of Patent: February 15, 2000Assignee: United Microelectronic Corp.Inventor: C. C. Hsue
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Patent number: 5981334Abstract: A method for fabricating DRAM capacitor which includes forming a transistor having a source/drain regions and a gate electrode above a silicon substrate; then, forming sequentially a stack of layers including a first insulating layer, a second insulating layer, a third insulating layer and a hard mask layer over the transistor; subsequently, patterning and etching the hard mask layer. Thereafter, an oxide layer is formed over the hard mask layer, and then portions of the layers are etched to form a capacitor region over the oxide layer and a contact opening exposing a portion of the source/drain region. In the subsequent step, a conducting layer is formed over the oxide layer, the hard mask layer, the sidewalls of the contact opening and the exposed portion of the source/drain region. Next, a polishing method is used to remove the conducting layer above the oxide layer, and then the oxide layer is removed to form a lower electrode.Type: GrantFiled: November 6, 1997Date of Patent: November 9, 1999Inventors: Sun-Chieh Chien, Jason Jenq, C. C. Hsue
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Patent number: 5310693Abstract: A method of forming a closely spaced self-aligned polysilicon pattern of conductive lines is achieved. The method involves forming semiconductor device structures in and on a semiconductor substrate. An insulating layer is formed over the device structures. An insulating layer structure is formed over the semiconductor device structures. A conductive polysilicon layer is formed over the insulating layer. A silicon oxide layer is formed over the polysilicon layer. The oxide layer is now patterned by lithography and etching. The patterning of the oxide layer leaves a first pattern of the oxide over a first designated plurality of polysilicon conductor lines and a second pattern between the oxide which exposes the polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between the first and second plurality of polysilicon conductor lines.Type: GrantFiled: June 24, 1993Date of Patent: May 10, 1994Assignee: United Microelectronics CorporationInventor: Peter C. C. Hsue
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Patent number: 5236853Abstract: A method of forming a closely spaced self-aligned polysilicon pattern of conductive lines is achieved. The method involves forming semiconductor device structures in and on a semiconductor substrate. An insulating layer is formed over the device structures. An insulating layer structure is formed over the semiconductor device structures. A conductive polysilicon layer is formed over the insulating layer. A silicon oxide layer is formed over the polysilicon layer. The oxide layer is now patterned by lithography and etching. The patterning of the oxide layer leaves a first pattern of the oxide over a first designated plurality of polysilicon conductor lines and a second pattern between the oxide which exposes the polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between the first and second plurality of polysilicon conductor lines.Type: GrantFiled: February 21, 1992Date of Patent: August 17, 1993Assignee: United Microelectronics CorporationInventor: Peter C. C. Hsue