Abstract: The invention relates to an electric arrangement, comprising: (a) functional modules, which can serve both as transaction initiators or transaction targets, whereby a transaction initiating functional module may need a transaction target functional module to execute a function for and on its behalf; (b) a first interconnect fabric connecting the functional modules and providing communication between those functional modules; wherein the (electric) arrangement being arranged in that a selected transaction initiation functional module has temporally exclusive access to transaction target functional module(s), executing a function for and on its behalf, to ensure that transaction initiating functional modules other than the selected transaction initiation functional module, have no uncontrolled access thereto, wherein said selected transaction initiation functional module being a hardware secure module.

Abstract: An input/output (IO) pad circuitry for integrated circuits (ICs) that is equipped with safety monitoring and control circuits to ensure that signals provided to/from the IO pad behave correctly. The IO pad circuitry allows monitoring of the IO pad signals, the detection of an undesired behavior, e.g., a wrong signal level or a wrong waveform. Furthermore, depending on a selected safety mode, a correction of the IO pad signals by overriding the monitored signal is further achieved. When in full safe mode, signals are provided as required, while in a partial safe mode only certain signals are provided depending on the status. A grouped safe mode allows providing a safe status to a group of IO pads using a single control. A monitoring circuitry between a plurality of input signals to an IC pad is also provided.

Abstract: An input/output (IO) pad circuitry for integrated circuits (ICs) that is equipped with safety monitoring and control circuits to ensure that signals provided to/from the IO pad behave correctly. The IO pad circuitry allows monitoring of the IO pad signals, the detection of an undesired behavior, e.g., a wrong signal level or a wrong waveform. Furthermore, depending on a selected safety mode, a correction of the IO pad signals by overriding the monitored signal is further achieved. When in full safe mode, signals are provided as required, while in a partial safe mode only certain signals are provided depending on the status. A grouped safe mode allows providing a safe status to a group of IO pads using a single control. A monitoring circuitry between a plurality of input signals to an IC pad is also provided.

Abstract: An apparatus for interfacing between a CPU and Flash memory units, enabling optimized sequential access to the Flash memory units. The apparatus interfaces between the address, control and data buses of the CPU and the address, control and data lines of the Flash memory units. The apparatus anticipates the subsequent memory accesses, and interleaves them between the Flash memory units. An optimization of the read access is therefore provided, thereby improving Flash memory throughput and reducing the latency. Specifically, the apparatus enables improved Flash access in embedded CPUs incorporated in a System-On-Chip (SOC) device.

Abstract: An apparatus for interfacing between a CPU and Flash memory units, enabling optimized sequential access to the Flash memory units. The apparatus interfaces between the address, control and data buses of the CPU and the address, control and data lines of the Flash memory units. The apparatus anticipates the subsequent memory accesses, and interleaves them between the Flash memory units. An optimization of the read access is therefore provided, thereby improving Flash memory throughput and reducing the latency. Specifically, the apparatus enables improved Flash access in embedded CPUs incorporated in a System-On-Chip (SOC) device.

Abstract: Apparatus and methods for video processing that integrate multiple processing modules that execute methods for simultaneous format conversion, scaling and image blending from a plurality of video sources, resulting in a video output ready for display. The modules use methods that are optimized for integration in pipeline architecture, enabling the processor to increase the number of video input sources while minimizing access to external memory. The processor combines multiple such pipelines, enabling the processor to simultaneously process a plurality of video inputs and combine these inputs into a single video output. The architecture is implemented as a hardware video processing apparatus.