Abstract: The present disclosure relates to a method of accessing a n-dimensional tensor of elements in a memory by a computer system. The multidimensional tensor comprises two-dimensional arrays, herein referred to as pages, each page being configured to comprise a predefined number of one-dimensional arrays of elements, herein referred to as sticks. The method includes linearly loading page per page of the tensor, and doing the following for each page: loading the non-empty sticks of the page from the memory using a base address of the page and determining a base address for the subsequent page using the number of loaded sticks and using an address offset indicative of potential empty sticks of the page. In case the number of loaded pages reaches a chunk size, the chunk page counter may be reinitialized and the linear loading may be continued with a subsequent page.

Abstract: An indication of a function to be executed is obtained, in which the function is one function of an instruction and configured to perform multiple operations. A determination is made of an operation of the multiple operations to be performed, and a set of function-specific parameters is validated using a set of values and a corresponding set of relationships. The set of values and corresponding set of relationships are based on the operation to be performed. One set of values and corresponding set of relationships are to be used for the operation to be performed, and another set of values and corresponding set of relationships are to be used for another operation of the multiple operations.

Abstract: A system for variable replacement in a template artificial intelligence (AI) accelerator code. The system includes: at least one memory; at least one processor communicatively coupled to the at least one memory, and configured for computing at least one table of variables from a template AI accelerator code; and an AI accelerator including a plurality of engines, and communicatively coupled to the at least one processor and the at least one memory. The AI accelerator is configured to create a variable replaced AI accelerator code for the plurality of engines of the AI accelerator from the template AI accelerator code by replacing variables in the template AI accelerator code with actual values from the at least one table of variables.

Abstract: Verifying the correctness of a leading zero counter, including: generating, based on an input value comprising a plurality of digits, a first bit vector, wherein each entry of the first bit vector indicates whether a corresponding digit of the input value is equal to zero; calculating, based on the first bit vector, a leading zero count for the input value; generating a bit mask comprising a number of leading ones equal to the leading zero count; generating a second bit vector comprising a one at a same index as a first occurring zero in the bit mask; and verifying the leading zero count based on the first bit vector and one or more of the bit mask and the second bit vector.

Abstract: Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.

Abstract: Reduced logic conversion of binary integers to binary coded decimals, including: generating, from an input binary integer, an intermediate value comprising all zero digits encoded in an intermediate format; until each bit of the input binary integer has been shifted into the intermediate value: shifting a bit of the input binary integer into the intermediate value; doubling the intermediate value; converting the intermediate value to a binary encoded decimal output; and wherein the intermediate format comprises, for each digit of the intermediate value, a plurality of bits corresponding to a plurality of even weights, a first bit corresponding to a one weight, and a second bit corresponding to an inverse of the one weight.

Abstract: A system for variable replacement in a template artificial intelligence (AI) accelerator code. The system includes: at least one memory; at least one processor communicatively coupled to the at least one memory, and configured for computing at least one table of variables from a template AI accelerator code; and an AI accelerator including a plurality of engines, and communicatively coupled to the at least one processor and the at least one memory. The AI accelerator is configured to create a variable replaced AI accelerator code for the plurality of engines of the AI accelerator from the template AI accelerator code by replacing variables in the template AI accelerator code with actual values from the at least one table of variables.

Abstract: A method, computer program, and computer system are provided for floating-point conversion with denormalization in a single clock cycle. An input floating-point number corresponding to an input data type is received. An exponent value and a fraction value are extracted from the received input floating-point number. A biasing constant associated with converting the received input floating-point number from the input data type to an output data type is determined. The exponent value is biased based on the biasing constant. The fraction value is converted to the output data type based on a denormalization constant associated with the extracted exponent value and the determined biasing constant. Biasing the exponent value and converting the fraction value occurs in a single clock cycle based on performing these actions in parallel. A floating-point number is output in the output data type corresponding to the converted fraction value and the biased exponent value.

Abstract: A hardware device is provided to perform a plurality of operations to convert an input value directly from one format to another format. The hardware device is to perform the plurality of operations based on execution of an instruction. The plurality of operations includes converting one part of the input value to provide a converted value, performing one or more arithmetic operations on another part of the input value to provide an intermediate value, and using the converted value and the intermediate value to provide a converted result in the other format. The converting, the performing and the using are performed as part of executing the instruction. The converted result in the other format is to be used in processing within the computing environment.

Abstract: A hardware device is provided to perform a plurality of operations to convert an input value directly from one format to another format. The hardware device is to perform the plurality of operations based on execution of an instruction. The plurality of operations includes scaling the input value to provide a scaled result and converting the scaled result from the one format to provide a converted result in the other format. The scaling and converting are to be performed as part of executing the instruction. The converted result in the other format is provided to be used in processing within the computing environment.

Abstract: Dynamic selection of a multiplication algorithm by receiving operands A and B, determining a difference between A and B, selecting a first multiplication algorithm if the difference falls below a threshold, selecting a second multiplication algorithm if the difference equals or exceeds the threshold, pre-scaling the operands, calculating a quotient for the scaled operands, back multiplying the quotient using the selected algorithm, yielding a product, subtracting the product from operand A, yielding a remainder, and providing the remainder as an output.

Abstract: Processing input data for transmittal to a data consumer such as an artificial intelligence engine is performed by arranging the input data into a uniform structure made up of sticks of data combined to form pages of sticks. A stick is any well-sized set of input data elements whereby the size of the stick is fixed. A masking pattern is established for sticks of data having certain ranges of invalid data for consumption of partial sticks while maintaining validity of the input data being transferred. The mask pattern is derived based on set-active-mask-and-value (SAMV) instructions. The derived mask pattern is carried forward for subsequent load instructions to the data consumer.

Abstract: A computer system configured to perform operations for validating memory access patterns of a static variant of a program instruction stream, the operations including randomizing a first set of input arguments, generating an address translation list for virtual addresses based on memory access patterns and storing memory accesses in a first table, and executing the static variant of the program instruction stream on the accelerator processing unit. During execution, the virtual addresses may be discarded and replaced by the addresses provided in the address translation list. The operations may include recording and storing every memory access of executing the static variant of the program instruction stream in a second table and comparing the memory access patterns stored in the second table to memory accesses patterns stored in the first table. Memory access patterns may be validated or discarded.

Abstract: An exception summary is provided for an invalid value detected during instruction execution. An indication that a value determined to be invalid was included in input data to a computation of one or more computations or in output data resulting from the one or more computations is obtained. The value is determined to be invalid due to one exception of a plurality of exceptions. Based on obtaining the indication that the value is determined to be invalid, a summary indicator is set. The summary indicator represents the plurality of exceptions collectively.

Abstract: A computer system configured to perform operations for validating memory access patterns of a static variant of a program instruction stream, the operations including randomizing a first set of input arguments, generating an address translation list for virtual addresses based on memory access patterns and storing memory accesses in a first table, and executing the static variant of the program instruction stream on the accelerator processing unit. During execution, the virtual addresses may be discarded and replaced by the addresses provided in the address translation list. The operations may include recording and storing every memory access of executing the static variant of the program instruction stream in a second table and comparing the memory access patterns stored in the second table to memory accesses patterns stored in the first table. Memory access patterns may be validated or discarded.

Abstract: An instruction is executed to perform a query function. The executing includes obtaining information relating to a selected model of a processor. The information includes at least one model-dependent data attribute of the selected model of the processor. The information is placed in a selected location for use by at least one application in performing one or more functions.

Abstract: A computer-implemented method, a computer system and a computer program product operate a secure code segment on a processor core of a processing unit, wherein the processing unit is configured with at least one processor core. The method comprises requesting exclusive secure execution of a secure code segment of the program code on the at least one processor core. The method also comprises setting the at least one processor core to exclusive secure execution for the secure code segment. The method further comprises executing the secure code segment on the at least one processor core uninterruptably. In addition, the method comprises wiping an architected state and a non-architected state of a physical processor core from the at least one processor core. Lastly, the method comprises setting the at least one processor core to the first execution mode for program code on the at least one processor core.

Abstract: A computer-implemented method, a computer system and a computer program product operate a secure code segment on a processor core of a processing unit, wherein the processing unit is configured with at least one processor core. The method comprises requesting exclusive secure execution of a secure code segment of the program code on the at least one processor core. The method also comprises setting the at least one processor core to exclusive secure execution for the secure code segment. The method further comprises executing the secure code segment on the at least one processor core uninterruptably. In addition, the method comprises wiping an architected state and a non-architected state of a physical processor core from the at least one processor core. Lastly, the method comprises setting the at least one processor core to the first execution mode for program code on the at least one processor core.

Abstract: Accessing a value M identifying M top levels of one or more N decision trees, wherein 1 ? M < Min(L1, ...., LN) and wherein a M top levels defines top nodes for each of the N decision trees, and wherein for each decision tree Ti of the N decision trees. Identifying one or more subtrees subtended by respective subsets of remaining nodes of each decision tree Ti, a remaining nodes including all of the nodes of said each decision tree Ti but its top nodes. Processing each of the K input records through a top nodes of said each decision tree Ti to associate each of the K input records with a single, respective one of the subtrees of each decision tree Ti, wherein K × N associations are obtained in total for the N decision trees and the K input records.

Abstract: A tensor representation of a machine learning inferences to be performed is built by forming complementary tensor subsets that respectively correspond to complementary subsets of one or more leaf nodes of one or more decision trees based on statistics of the one or more leaf nodes of the one or more decision trees and data capturing attributes of one or more split nodes of the one or more decision trees and the one or more leaf nodes of the decision trees. The complementary tensor subsets are ranked such that a first tensor subset and a second tensor subset of the complementary tensor subsets correspond to a first leaf node subset and a second leaf node subset of the complementary subsets of the one or more leaf nodes.