Patents by Inventor Cédric MARCHAND
Cédric MARCHAND has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11545998Abstract: Embodiments of the invention provide an elementary check node processing unit (300) implemented in a check node processing unit of a non-binary error correcting code decoder, the elementary check node processing unit (300) being linked to a variable node processing unit (305) and being configured to receive a first message and a second message, each message comprising at least two components. The elementary check node processing unit (300) comprises a calculation unit (301) which determines two or more auxiliary components from the components comprised in the first message and from the components comprised in the second message, an auxiliary component comprising an auxiliary reliability metrics. The calculation unit (301) also determines, in association with each of the two or more auxiliary components, decoding performance values.Type: GrantFiled: October 7, 2019Date of Patent: January 3, 2023Inventors: Hassan Harb, Emmanuel Boutillon, Cédric Marchand
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Patent number: 11476870Abstract: Embodiments of the invention provide a variable node processing unit for a non-binary error correcting code decoder, the variable node processing unit being configured to receive one check node message and intrinsic reliability metrics, and to generate one variable node message from auxiliary components derived from said one check node message and intrinsic reliability metrics, the intrinsic reliability metrics being derived from a received signal, an auxiliary component comprising an auxiliary symbol and an auxiliary reliability metrics associated with said auxiliary symbol, wherein the variable node processing unit comprises: a sorting and redundancy elimination unit configured to process iteratively the auxiliary components and to determine components of the variable node message by iteratively sorting the auxiliary components according to a given order of the auxiliary reliability metrics and keeping a predefined number of auxiliary components comprising the auxiliary symbols that are the most reliableType: GrantFiled: July 4, 2019Date of Patent: October 18, 2022Assignee: UNIVERSITE DE BRETAGNE SUDInventors: Emmanuel Boutillon, Cédric Marchand, Hassan Harb
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Patent number: 11290128Abstract: Embodiments of the invention provide a decoder comprising at least one check node processing unit configured to receive at least three variable node messages from one or more variable node processing units and to determine one or more check node messages, wherein the at least one check node processing unit comprises at least two blocks of sub-check nodes, each block of sub-check node being configured to: determine a set of sub-check node syndromes from at least one variable node message among the at least three variable node messages; and determine at least one check node message from at least one syndrome.Type: GrantFiled: June 7, 2018Date of Patent: March 29, 2022Assignee: UNIVERSITE DE BRETAGNE SUDInventors: Cédric Marchand, Emmanuel Boutillon
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Patent number: 11245421Abstract: A sorting device and method for determining elementary check node components in an elementary check node processor implemented in a non-binary error correcting code decoder by sorting auxiliary components are presented. The auxiliary components are stored in a plurality of FIFO memories, each FIFO memory being assigned a FIFO number index. Each auxiliary component stored in a given FIFO memory comprises an auxiliary symbol, a reliability metrics representing the reliability of the auxiliary symbol, and the FIFO number index assigned to the given FIFO memory. The sorting device is configured to sort the auxiliary components by a plurality of multiplexers arranged sequentially. Each multiplexer is configured to initialize a candidate elementary check node component from the components of a FIFO memory corresponding to the auxiliary component which comprise the most reliable auxiliary symbol and to perform one or more iterations of the illustrated receiving, updating and sorting steps.Type: GrantFiled: July 4, 2019Date of Patent: February 8, 2022Assignee: UNIVERSITE DE BRETAGNE SUDInventors: Emmanuel Boutillon, Cédric Marchand, Hassan Harb
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Publication number: 20220038116Abstract: Embodiments of the invention provide an elementary check node processing unit (300) implemented in a check node processing unit of a non-binary error correcting code decoder, the elementary check node processing unit (300) being linked to a variable node processing unit (305) and being configured to receive a first message and a second message, each message comprising at least two components. The elementary check node processing unit (300) comprises a calculation unit (301) which determines two or more auxiliary components from the components comprised in the first message and from the components comprised in the second message, an auxiliary component comprising an auxiliary reliability metrics. The calculation unit (301) also determines, in association with each of the two or more auxiliary components, decoding performance values.Type: ApplicationFiled: October 7, 2019Publication date: February 3, 2022Applicant: UNIVERSITE DE BRETAGNE SUDInventors: Hassan HARB, Emmanuel BOUTILLON, Cédric MARCHAND
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Patent number: 11133827Abstract: Embodiments of the invention provide a check node processing unit configured to determine at least one check node message to decode a signal encoded using a NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units to determine permuted variable node messages by applying permutations to at least three variable node messages generated by variable node processing units; a syndrome calculation unit to determine a set of syndromes comprising binary values from the permuted variable node messages; a decorrelation and permutation unit configured, for each check node message of a given index, to: determine a permuted index by applying the inverse of the one or more permutations; select at least one valid syndrome in the set of syndromes; and determine at least one candidate check node component; and a selection unit to determine at least one check node message from the candidate check node component.Type: GrantFiled: June 7, 2018Date of Patent: September 28, 2021Assignee: UNIVERSITE DE BRETAGNE SUDInventors: Emmanuel Boutillon, Cédric Marchand
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Patent number: 11095308Abstract: A check node processing unit configured to determine check node messages to decode a signal encoded using NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units configured to determine permuted variable node messages by permuting variable node messages generated by one or more variable node processing units; a syndrome sub-check node configured to determine check node messages from a set of syndromes, the set of syndromes being determined from one or more intermediate messages computed from the permuted variable node messages; a forward-backward sub-check node configured to determine permuted check node messages from the intermediate messages; a switching unit configured to generate check node messages of given index from the check node messages or from the permuted check node messages depending on the giving index.Type: GrantFiled: June 7, 2018Date of Patent: August 17, 2021Assignee: UNIVERSITE DE BRETAGNE SUDInventors: Cédric Marchand, Emmanuel Boutillon
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Publication number: 20210250047Abstract: A sorting device for determining elementary check node components in an elementary check node processor (3) implemented in a non-binary error correcting code decoder by sorting auxiliary components. The auxiliary components are stored in a plurality of FIFO memories (33-n), each FIFO memory (33-n) being assigned a FIFO number index. Each auxiliary component stored in a given FIFO memory (33-n) comprises an auxiliary symbol, a reliability metrics representing the reliability of the auxiliary symbol, and the FIFO number index assigned to the given FIFO memory (33-n). The sorting device is configured to sort the auxiliary components by a plurality of multiplexers (34-m) arranged sequentially.Type: ApplicationFiled: July 4, 2019Publication date: August 12, 2021Applicant: UNIVERSITE DE BRETAGNE SUDInventors: Emmanuel BOUTILLON, Cédric MARCHAND, Hassan HARB
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Publication number: 20210167799Abstract: Embodiments of the invention provide a variable node processing unit (31) for a non-binary error correcting code decoder, the variable node processing unit (31) being configured to receive one check node message and intrinsic reliability metrics, and to generate one variable node message from auxiliary components derived from said one check node message and intrinsic reliability metrics, the intrinsic reliability metrics being derived from a received signal, an auxiliary component comprising an auxiliary symbol and an auxiliary reliability metrics associated with said auxiliary symbol, wherein the variable node processing unit (31) comprises: a sorting and redundancy elimination unit (313) configured to process iteratively the auxiliary components and to determine components of the variable node message by iteratively sorting the auxiliary components according to a given order of the auxiliary reliability metrics and keeping a predefined number of auxiliary components comprising the auxiliary symbols thatType: ApplicationFiled: July 4, 2019Publication date: June 3, 2021Applicant: UNIVERSITE DE BRETAGNE SUDInventors: Emmanuel BOUTILLON, Cédric MARCHAND, Hassan HARB
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Publication number: 20210143838Abstract: Embodiments of the invention provide a decoder comprising at least one check node processing unit configured to receive at least three variable node messages from one or more variable node processing units and to determine one or more check node messages, wherein the at least one check node processing unit comprises at least two blocks of sub-check nodes, each block of sub-check node being configured to: determine a set of sub-check node syndromes from at least one variable node message among the at least three variable node messages; and determine at least one check node message from at least one syndrome.Type: ApplicationFiled: June 7, 2018Publication date: May 13, 2021Applicant: UNIVERSITE DE BRETAGNE SUDInventors: Cédric MARCHAND, Emmanuel BOUTILLON
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Publication number: 20200177203Abstract: Embodiments of the invention provide a check node processing unit (25-cn) configured to determine at least two check node messages in a decoder to decode a signal encoded using a NB-LDPC code, the check node processing unit comprising: data link to one or more message presorting units (24-cn) configured to determine at least three permuted variable node messages by permuting at least three variable node messages generated by one or more variable node processing units (23), each variable node message comprising components, a component comprising a symbol and a reliability metrics associated with said symbol; a syndrome sub-check node (31) configured to determine check node messages from a set of syndromes, the set of syndromes being determined from one or more intermediate messages computed from the at least three permuted variable node messages; a forward-backward sub-check node (32) configured to determine permuted check node messages at least from one of said one or more intermediate messages; a switchinType: ApplicationFiled: June 7, 2018Publication date: June 4, 2020Applicant: UNIVERSITE DE BRETAGNE SUDInventors: Cédric MARCHAND, Emmanuel BOUTILLON
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Patent number: 10637510Abstract: Devices and methods for decoding a signal encoded using an error correcting code are provided. For example, a check node processing unit is provided for a decoder to receive at least two input messages and to generate at least one output message, each message comprising a plurality of components. The check node processing unit comprises a data structure configured to store the input messages, the components of the input messages being associated with an integer index. The check node processing unit also comprises a data processing unit configured to apply one or more iterations of a transformation operation to at least a part of the data structure depending on at least some of the components of the input messages associated with a given value of the integer index, which provides a transformed data structure. The check node processing unit further comprises a calculation unit configured to determine at least one output message from the transformed data structure.Type: GrantFiled: April 27, 2017Date of Patent: April 28, 2020Assignee: UNIVERSITE DE BRETAGNE SUDInventors: Cédric Marchand, Emmanuel Boutillon
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Publication number: 20200127683Abstract: Embodiments of the invention provide a check node processing unit (25) configured to determine at least one check node message to decode a signal encoded using a NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units (24) configured to determine permuted variable node messages by applying one or more permutations to at least three variable node messages generated by one or more variable node processing units (23); a syndrome calculation unit (26) configured to determine a set of syndromes from the at least three permuted variable node messages, a syndrome comprising binary values; a decorrelation and permutation unit (27) configured, for each check node message of a given index, to: Determine a permuted index by applying to said given index the inverse of the one or more permutations; Select at least one valid syndrome in the set of syndromes, a valid syndrome comprising a binary value associated with said permuted index equal to a given value; DetermiType: ApplicationFiled: June 7, 2018Publication date: April 23, 2020Applicant: UNIVERSITE DE BRETAGNE SUDInventors: Emmanuel BOUTILLON, Cédric MARCHAND
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Patent number: 10560120Abstract: At least a method and an apparatus are presented to decode a signal encoded using an error correcting code. For example, a decoder comprising a check node processing unit is presented. The check node processing unit is configured to receive at least three input messages and to generate at least one output message. A syndrome calculator is configured to determine a set of syndromes from the at least three input messages using at least two elementary check node processors. A decorrelation unit is configured to determine, in association with at least an output message, a set of candidate components from the set of syndromes. A selection unit is configured to determine at least an output message by selecting components comprising distinct symbols from the set of candidate components associated with the at least an output message.Type: GrantFiled: September 1, 2017Date of Patent: February 11, 2020Assignee: UNIVERSITE DE BRETAGNE SUDInventors: Cédric Marchand, Emmanuel Boutillon
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Patent number: 10476523Abstract: At least a method and an apparatus are presented for decoding a signal. For example, a decoder is presented for determining an estimate of an encoded signal. The decoder comprises one or more variable node processing units and one or more check node processing units configured to exchange messages, each message comprising one or more components, a component comprising a symbol and a reliability metric associated with the symbol. The at least one check processing unit is further configured to calculate at two or more elementary check node processors a set of syndromes from at least three permuted messages, a syndrome comprising a binary vector; generate at least one check node message from the set of syndromes depending on the binary vector, and send the at least one check node message to a signal estimation unit.Type: GrantFiled: October 3, 2017Date of Patent: November 12, 2019Assignee: UNIVERSITE DE BRETAGNE SUDInventors: Cédric Marchand, Emmanuel Boutillon
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Publication number: 20180115323Abstract: Embodiments of the invention provide a decoder for determining an estimate of an encoded signal, the decoder comprising one or more variable node processing units (23) and one or more check node processing units (25) configured to exchange messages, each message comprising one or more components, a component comprising a symbol and a reliability metric associated with said symbol, wherein the decoder comprises: at least one vector permutation unit (24) configured to receive a set of at least three variable node messages comprising variable node components from at least one variable node processing unit and to generate permuted messages depending on a plurality of the reliability metrics comprised in said variable node components, the variable node messages being sorted according to an order of the reliability metrics; and at least one check node processing unit (25-1) configured to: calculate at two or more elementary check node processors (26) a set of syndromes from said at least three permuted messagesType: ApplicationFiled: October 3, 2017Publication date: April 26, 2018Applicant: UNIVERSITE DE BRETAGNE SUDInventors: Cédric MARCHAND, Emmanuel BOUTILLON
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Publication number: 20180076830Abstract: Embodiments of the invention provide a check node processing unit implemented in a decoder for decoding a signal, the check node processing unit being configured to receive at least three input messages and to generate at least one output message, wherein the check node processing unit comprises: a syndrome calculator (31) configured to determine a set of syndromes from said at least three input messages using at least two elementary check node processors (311), each syndrome comprising a symbol, a reliability metric associated with said symbol, and a binary vector; a decorrelation unit (33) configured to determine, in association with at least an output message, a set of candidate components from said set of syndromes, each candidate component comprising a symbol and a reliability metric associated with said symbol, said set of candidate components comprising one or more pairs of components comprising a same symbol; and a selection unit (35) configured to determine at least an output message by selectingType: ApplicationFiled: September 1, 2017Publication date: March 15, 2018Applicant: UNIVERSITE DE BRETAGNE SUDInventors: Cédric MARCHAND, Emmanuel BOUTILLON
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Publication number: 20170317695Abstract: Embodiments of the invention provide a check node processing unit implemented in a decoder, said decoder being configured to decode a signal encoded using an error correcting code, said signal comprising symbols, the check node processing unit being configured to receive at least two input messages and to generate at least one output message, each message comprising a plurality of components, each component comprising a value of a symbol and a reliability metrics associated with said symbol, wherein the check node processing unit comprises: a data structure (31) configured to store said input messages, the components of the input messages being associated with an integer index in the data structure; a data processing unit (33) configured to apply one or more iterations of a transformation operation to at least a part of the data structure, each iteration of the transformation operation being performed to arrange the components of said input messages in said data structure (31) depending on at least some ofType: ApplicationFiled: April 27, 2017Publication date: November 2, 2017Applicant: UNIVERSITE DE BRETAGNE SUDInventors: Cédric MARCHAND, Emmanuel BOUTILLON