Abstract: Asynchronous sample rate conversion is performed using a noise-shaped numerically controlled oscillator (204,420) that generates a clock (207,428) that is synchronous to the system clock (217,424) but having a time average frequency that is equal to a multiple (X) of the asynchronous sample rate frequency required for the conversion. Unwanted spectral energy in the generated clock (207,428) is noise-shaped out of the pass-band and so does not degrade signal performance. For digital-to-analog conversion, the generated clock (207) is used to time an interpolation (206) of digital data (DATAFs) by an multiple X to produce an interpolated signal (DATAFsX) having a time average rate equal to the over-sampling frequency but being synchronized with the system clock (217). The interpolated signal (DATAFsX) is then converted (216) to an analog signal using a derivative of the system clock (217), or can be output as digital data at the rate derived from the system clock.

Abstract: An amplitude adjust circuit (10) provides a scaled representation (36) of an analog audio signal (28) with substantially zero DC offset relative to a reference voltage. A voltage reference generator (12) produces a voltage reference (20) that inputs to an operational amplifier (14). The offsetting circuit (16) offsets an analog audio signal (28) by a DC component substantially equal to the voltage reference (20) and provides the result as an input to the operational amplifier (14). The operational amplifier (14) produces an output with a DC component substantially equal to the voltage reference (20). The impedance network (18) operably couples to the operational amplifier (14) output and to the voltage reference (20) so that both sides of the impedance network (18) are held at the voltage reference (20) level.

Abstract: A sigma-delta analog-to-digital converter (ADC) (80) includes first (81) and second (82) integrators, a quantizer (83) connected to an output of the second integrator (82), and a feedback circuit (84) connected to the output of the quantizer (83). In order to avoid the effects of delays through actual circuit elements, the feedback circuit (84) keeps the feedback signal to the first integrator (81) in a high-impedance state until the quantizer (83) resolves the output of the second integrator (82). Thus, the first integrator (81) avoids temporarily summing a possibly incorrect feedback signal. In addition, the feedback circuit (84) also keeps the first integrator (81) from integrating a sum of an input signal and the feedback signal until the feedback signal is driven to its correct state in response to the output of the quantizer (83). To accomplish these results, the feedback circuit (84) includes a compensation circuit (151) for continually determining when the quantizer (83) resolves.