Abstract: A blending apparatus includes a blending jar and a lid. The blending jar has an internal surface defining an internal volume, and a mixing blade positioned within the internal volume. The lid is releasably mounted to the blending jar and includes at least one scraper extending into the internal volume. The at least one scraper is adjacent to the internal surface of the blending jar and is arranged and configured to disrupt rotational flow of food particles within the internal volume and/or scrape food particles from an inner surface of the blending jar.

Abstract: Lightweight, small, portable devices and methods are disclosed that provide oxygen-enriched air using an ultra rapid adsorption cycle based on advanced molecular sieve materials.

Abstract: A blending apparatus includes a blending jar and a lid. The blending jar has an internal surface defining an internal volume, and a mixing blade positioned within the internal volume. The lid is releasably mounted to the blending jar and includes at least one scraper extending into the internal volume. The at least one scraper is adjacent to the internal surface of the blending jar and is arranged and configured to disrupt rotational flow of food particles within the internal volume and/or scrape food particles from an inner surface of the blending jar.

Abstract: A blending apparatus includes a blending jar and a lid. The blending jar has an internal surface defining an internal volume, and a mixing blade positioned within the internal volume. The lid is releasably mounted to the blending jar and includes at least one scraper extending into the internal volume. The at least one scraper is adjacent to the internal surface of the blending jar and is arranged and configured to disrupt rotational flow of food particles within the internal volume and/or scrape food particles from an inner surface of the blending jar.

Abstract: Lightweight, small, portable devices and methods are disclosed that provide oxygen-enriched air using an ultra rapid adsorption cycle based on advanced molecular sieve materials.

Abstract: Lightweight, small, portable devices and methods are disclosed that provide oxygen-enriched air using an ultra rapid adsorption cycle based on advanced molecular sieve materials.

Abstract: Lightweight, small, portable devices and methods are disclosed that provide oxygen-enriched air using an ultra rapid adsorption cycle based on advanced molecular sieve materials.

Abstract: Lightweight, small, portable devices and methods are disclosed that provide oxygen-enriched air using an ultra rapid adsorption cycle based on advanced molecular sieve materials.

Abstract: Lightweight, small, portable devices and methods are disclosed that provide oxygen-enriched air using an ultra rapid adsorption cycle based on advanced molecular sieve materials.

Abstract: A blending apparatus includes a blending jar and a lid. The blending jar has an internal surface defining an internal volume, and a mixing blade positioned within the internal volume. The lid is releasably mounted to the blending jar and includes at least one scraper extending into the internal volume. The at least one scraper is adjacent to the internal surface of the blending jar and is arranged and configured to disrupt rotational flow of food particles within the internal volume and/or scrape food particles from an inner surface of the blending jar.

Abstract: A reticulated polyurethane foam having a density less than 1.0 pounds per cubic foot [16 kg/m3] forms an explosion suppressing material that is installed into the inner volume of a fuel tank to fill from 50 to 90% or up to 100% of the volume of such tank. The reticulated polyurethane foam has particular advantage when used in a fuel tank for an aircraft.

Abstract: A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of a second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input.

Abstract: A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of n second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth-multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input.

Abstract: A logic module includes a first and a second two-input multiplexer each having first and second data inputs. Both the first and second multiplexer include a select input, both of which are connected to the output of a two-input logic gate of a first type having first and second data inputs. The inputs to the first and second two-input multiplexers are sourced with data signals from a first group. One input of each of the logic gates is sourced from a data signal of a second group and the other input of each of the logic gates is sourced from a data signal of a third group. A third two-input multiplexer has its first and second data inputs connected the outputs of the first and second multiplexers, respectively. A select input of the third two-input multiplexer is connected to the output of a two input logic gate of a second type having first and second data inputs.

Abstract: A method for simultaneously programming a plurality of antifuses each having a first electrode connected to a common node and each having a second electrode connected to an isolated node electrically isolated from the nodes of each of the other antifuses includes the steps of precharging the common node and the isolated nodes to an intermediate voltage potential selected to minimize the stress on all antifuses; precharging the isolated nodes of selected ones of the antifuses to a first programming voltage potential placing a second programming voltage potential on said common node, the first and second programming voltage potentials selected such that the difference between them is sufficient to cause programming of said antifuses and such that said intermediate potential is substantially centered between them, waiting a predetermined amount of time; and measuring the current flowing between the common node isolated nodes.

Abstract: A method for isolating a first low-voltage circuit node comprising an output of a low-voltage device from a second circuit node which carries high programming voltages during programming of user-programmable interconnect elements includes the step of raising the normal power supply voltage provided to the low-voltage devices to an intermediate level lower than the programming voltage but high enough to protect the outputs of the low voltage devices from damage. The output to be protected is caused to assume a desired state and is then inhibited from changing state during the programming cycle. Programming voltage is then applied to the low voltage circuit node.

Abstract: A circuit for preventing false programming of unselected anti-fuses in an anti-fuse array includes a series impedance including a plurality of transistors which may be used for partial address selection connected between a source of programming voltage and a bit line.

Abstract: A semiconductor or substrate of a first conductivity type includes a well structure of a second conductivity type formed therein. A first low voltage MOS transistor includes spaced apart source and drain regions of the first conductivity type in the well. A first transistor gate lies above a channel region which is disposed between the source and drain regions of the first low voltage MOS transistor and is separated therefrom by a gate dielectric having a first thickness. A second high voltage transistor includes spaced apart source and drain regions of the first conductivity type in the well. A second transistor gate lies above a channel region which is disposed between the source and drain regions of the second high voltage transistor and is separated therefrom by a gate dielectric having a second thickness which is greater than the thickness of the gate dielectric of the first low voltage MOS transistor.

Abstract: A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of a second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input.

Abstract: The present invention includes four approaches to reduce the unintended programming of antifuses while programming selected antifuses and to decrease the programming time. The first approach includes circuitry to maintain the voltage placed on unselected antifuses at a constant level by use of a voltage source. According to the second approach, a resistor is included in series with the voltage source. According to the third approach, a diode is included in series with the voltage source. According to the fourth approach, a MOS implementation of a diode is included in series with the voltage source.