Abstract: Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer.

Abstract: A method is presented for constructing fully-aligned top-via interconnects by employing a subtractive etch process. The method includes building a first metallization stack over a substrate, depositing a first lithography stack over the first metallization stack, etching the first lithography stack and the first metallization stack to form a receded first metallization stack, and depositing a first dielectric adjacent the receded first metallization stack. The method further includes building a second metallization stack over the first dielectric and the receded first metallization stack, depositing a second lithography stack over the second metallization stack, etching the second lithography stack and the second metallization stack to form a receded second metallization stack, and trimming the receded first metallization stack to form a via connecting the receded first metallization stack to the receded second metallization stack.

Abstract: Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer.

Abstract: Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer.

Abstract: Integrated chips and methods of forming the same include forming upper dummy lines over lower conductive lines. The lower conductive lines are recessed to form conductive vias between the lower conductive lines and the upper dummy lines. The upper dummy lines are replaced with upper conductive lines that contact the conductive vias.

Abstract: A method is presented for constructing fully-aligned top-via interconnects by employing a subtractive etch process. The method includes building a first metallization stack over a substrate, depositing a first lithography stack over the first metallization stack, etching the first lithography stack and the first metallization stack to form a receded first metallization stack, and depositing a first dielectric adjacent the receded first metallization stack. The method further includes building a second metallization stack over the first dielectric and the receded first metallization stack, depositing a second lithography stack over the second metallization stack, etching the second lithography stack and the second metallization stack to form a receded second metallization stack, and trimming the receded first metallization stack to form a via connecting the receded first metallization stack to the receded second metallization stack.

Abstract: Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer.

Abstract: Integrated chips and methods of forming the same include forming upper dummy lines over lower conductive lines. The lower conductive lines are recessed to form conductive vias between the lower conductive lines and the upper dummy lines. The upper dummy lines are replaced with upper conductive lines that contact the conductive vias.

Abstract: Air-gap containing metal interconnects with selectively-deposited dielectric material are provided. In one aspect, a method of forming an interconnect structure with air-gaps includes: forming interconnect metal lines separated from a first dielectric by a liner and a barrier layer; depositing a capping layer and an inhibitor layer over the interconnect metal lines; patterning the capping layer, inhibitor layer and first dielectric to form the air-gaps between the interconnect metal lines; selectively depositing a second dielectric to form a bridge of the second dielectric over/pinching off the air-gaps, wherein the barrier layer inhibits deposition of the second dielectric along the sidewalls of the interconnect metal lines, and the inhibitor layer inhibits deposition of the second dielectric on top of the interconnect metal lines. An interconnect structure is also provided.

Abstract: Air-gap containing metal interconnects with selectively-deposited dielectric material are provided. In one aspect, a method of forming an interconnect structure with air-gaps includes: forming interconnect metal lines separated from a first dielectric by a liner and a barrier layer; depositing a capping layer and an inhibitor layer over the interconnect metal lines; patterning the capping layer, inhibitor layer and first dielectric to form the air-gaps between the interconnect metal lines; selectively depositing a second dielectric to form a bridge of the second dielectric over/pinching off the air-gaps, wherein the barrier layer inhibits deposition of the second dielectric along the sidewalls of the interconnect metal lines, and the inhibitor layer inhibits deposition of the second dielectric on top of the interconnect metal lines. An interconnect structure is also provided.

Abstract: An agent-based modeling system (ABMS) is employed to quantitatively analyze individual components of each system of the coagulation-immune/inflammatory-fibrinolysis system at every point of simulation. ABMS is a dynamic modeling and simulation tool that allows the study of dynamic non-linear networked systems. ABMS represents a non-reductionist approach of studying the biologic process as a whole, while retaining information at the level of an individual component.

Abstract: A clock tree synthesizer calculates balanced cluster sets of nodes a particular level of a clock tree in a circuit description based on a set of available buffer types. Each balanced cluster set is tested to see if it meets a design constraint. If the design constraint is not met for a particular balanced cluster set, the particular cluster set is removed from consideration in the clock tree solution. For the cluster sets that do meet the design constraint, a cost associated with each cluster set is calculated. A balanced cluster set that has the lowest cost is selected for the clock tree solution. In one embodiment, the lowest cost balanced cluster set for one level in the clock tree forms the nodes for the next higher level in the clock tree, and the process is repeated at each level of the clock tree up to a root node.

Abstract: A near-field optical or MO data storage system uses an optical focusing device for focusing an incident optical beam to a small size focal spot. The optical focusing device includes an optically transmissive body which is defined by a generally flat incident surface, a flat, bottom surface disposed opposite and parallel to the incident surface, and a reflective side coated with a reflective layer for reflecting the optical beam through the body toward the bottom surface. The bottom surface defines a focal plane on which the focal spot is formed, for generating a localized evanescent field. The focal spot is located along a central axis P, in very close proximity to the data storage disk, such that the localized evanescent field interacts with the disk, for enabling data to be transduced to and from the disk by effecting near field coupling. An electro-magnetic coil or coil assembly, can optionally be formed on the bottom surface, co-axially with the focal spot, for generating a desired write magnetic field.

Abstract: The method of making and self-aligning a magneto-optical head at a wafer level is as follows: A flat optical substrate is molded or heat pressed in batches as a wafer level to form the desired lens shapes. Coil cavities or depressions are simultaneously formed with the lens to accommodate the coil assembly. Conductive plugs are formed in proximity to the cutting lines, for wire bonding attachment to the coil. The plugs are filled with a conductive material such as copper. The plugs do not extend through the entire depth of the optical wafer, thus further facilitating the mass production of the integrated heads. The slider body wafer is formed from silicon or other appropriate material. The slider body wafer and the lens/coil wafer are bonded. Coils and pedestals are formed on the lens / coil plate using thin-film processing techniques. Reflective surfaces are deposited on the bottom surface of the substrate, opposite the lens. The mirror material around the pedestal areas and plugs is masked and removed.

Abstract: A read/write head is structurally significantly less complicated than optical reading devices, requires minimal or no optical alignment, capable of writing at higher track densities, and has better control of the data and servo tracks than conventional magnetic heads. The head is also capable of using an available heat source and a relatively weak magnetic field, such as 300 Oersteds, to write data on a data storage medium. The combination of a magnetic read sensor with a near field magneto-optical (MO) write element creates a hybrid read/write head capable of high density recording with a high signal to noise ratio. The integration of the MO write element can be accomplished by various alternative or complementary methods. One method is to mount a heat source, such as a laser or light source on a slider with minimal or no additional optical components.

Abstract: A holographic scanning system for scanning a bar code indicia is disclosed in which the light beam of a laser is split into two segments, each directed through a plurality of holograms mounted on a single rotating disk for generating a scanning pattern comprising a plurality of intersecting lines on a target area through which passes a label or object bearing a bar code indicia. The light reflected from the bar code indicia is picked up by an optical detector for use in reading the bar code. A second embodiment includes a rotating disk having mounted thereon two holograms each offset to the other which generates a semicircular scan pattern used in generating an X scan pattern on the target area.