Abstract: A SOC (Substrate-On-Chip) packaging process is disclosed. A layer of two-stage thermosetting mixture with solvent is coating on an upside of a substrate. Thereafter, the substrate is heated for removing solvent so that the two-stage thermosetting mixture becomes a B-stage dry adhesive film without solvent. Thus, the bonding pads of the chip are not covered by the dry adhesive film and a better operating flexibility is obtained in the SOC packaging process.

Abstract: A thermal cell has an infrared source element for producing an infrared signal and a spatial decorrelator element which spatially decorrelates the generated infrared signal to increase the fill factor of the thermal cell. The infrared source element includes an infrared generating cell, with a resistive element. The spatial decorrelator element is disposed above and spaced apart from the infrared source element and has an aperture formed therein and through which the infrared signal radiates. The aperture extends substantially orthogonal to the primary surface of the source element and between primary surfaces of the decorrelator element, which are in turn substantially parallel with the source element primary surface. The side walls of the aperture reflect the infrared signal.