Abstract: A computer system comprising a plurality of processor units, resources for executing a harmonic set of tasks, and a task interrupt switch device having inputs for receiving a common time base and the task interrupts, outputs each connected to a respective one of the processor units, registers each corresponding a to respective one of the outputs, reinitializable counters each corresponding to a respective one of the outputs, and a control unit arranged to distribute the task interrupts between the outputs as a function of the values of the registers and of the counters.

Abstract: A computer system comprising a plurality of processor units, resources for executing a harmonic set of tasks, and a task interrupt switch device having inputs for receiving a common time base and the task interrupts, outputs each connected to a respective one of the processor units, registers each corresponding a to respective one of the outputs, reinitializable counters each corresponding to a respective one of the outputs, and a control unit arranged to distribute the task interrupts between the outputs as a function of the values of the registers and of the counters.

Abstract: A flight control system of an aircraft including a first processing unit, a second processing unit, communication means configured to establish a first two-way digital link and as second two-way digital link between the first processing unit and the second processing unit. The second link is redundant with the first link, and the first link and second link are likely to be active concomitantly. The system further includes backup communication means enabling data exchanges between the first processing unit and the second processing unit in the case of a failure in the first link and second link. The backup communication means includes an array of sensors or actuators and/or a secure onboard network for the avionics.

Abstract: The present invention concerns a method for switching, by a local processing unit (1,2) of a flight control system of an aircraft, configured to control at least one local actuator, connected to at least one local sensor and connected via at least one link (3,4) to an opposite processing unit (2,1) configured to control at least one opposite actuator and be connected to at least one opposite sensor, said local processing unit (1,2) being further configured to be connected to backup communication means (13,14) enabling data exchanges between the local processing unit (1,2) and the opposite processing unit (2,1) in the case of failures of the links connecting same (3,4), said backup communication means comprising an array of sensors or actuators (13) and/or a secure onboard network for the avionics (14), comprising steps of: •—sending, to the opposite processing unit (2,1), acquisition data relative to the at least one local sensor and actuator data relative to the at least one local actuator, •—receiving, from

Abstract: The invention concerns a system on a chip (100) comprising a set of master modules which includes a main processing module (101a) and a direct memory access controller (DMA) (102a) associated with said module (101a), and at least one secondary processing module (101b) and a DMA (102b) associated with said module (101b), and slave modules; each master module being configured for connection to a clock source, a power supply, and slave modules which include a set of proximity peripherals (105a,b), at least one internal memory (104a,b) and a set (106) of peripherals and external memories shared by the master modules; said clock source, power supply, proximity peripherals (105a,b) and a cache memory (103a,b) of a master processing module and its DMA being dedicated to said master processing module and not shared with the other processing modules of the set of master modules; and said at least one internal memory (104a,b) of each master processing module and its DMA being dedicated to said master processing module,

Abstract: The present invention concerns a method for switching, by a local processing unit (1,2) of a flight control system of an aircraft, configured to control at least one local actuator, connected to at least one local sensor and connected via at least one link (3,4) to an opposite processing unit (2,1) configured to control at least one opposite actuator and be connected to at least one opposite sensor, said local processing unit (1,2) being further configured to be connected to backup communication means (13,14) enabling data exchanges between the local processing unit (1,2) and the opposite processing unit (2,1) in the case of failures of the links connecting same (3,4), said backup communication means comprising an array of sensors or actuators (13) and/or a secure onboard network for the avionics (14), comprising steps of: •—sending, to the opposite processing unit (2,1), acquisition data relative to the at least one local sensor and actuator data relative to the at least one local actuator, •—receiving, from

Abstract: The present invention concerns a flight control system of an aircraft comprising: —a first processing unit (1), —a second processing unit (2), —communication means configured to establish a first two-way digital link (3) and a second two-way digital link (4) between the first processing unit (1) and the second processing unit (2), said second link (4) being redundant with the first link (3), and said first link (3) and second link (4) being likely to be active concomitantly, said system further comprising backup communication means enabling data exchanges between the first processing unit (1) and the second processing unit (2) in the case of a failure in the first link (3) and second link (4), said backup communication means comprising an array of sensors or actuators (13) and/or a secure onboard network for the avionics (14).

Abstract: The invention concerns a bandwidth control method in an on-chip system comprising at least one main master module, at least one secondary master module, at least one slave module and a bus connected to each module on a communication link, the bus comprising interconnection means to make at least one common slave module communicate with at least one main master module and with at least one secondary master module via at least one common path portion, the method comprising the following steps carried out for each common slave module: first detection of a first request to access the common slave module, issued by a main master module, definition of a blocking time Dj associated with the common slave module, blocking, during blocking time Dj, of any data transfer on the at least one common path portion between a secondary master module and the common slave module.

Abstract: The invention in particular concerns a method for filtering access to an on-chip system comprising at least one master module, at least one slave module and a bus, the bus comprising at least one slave port, at least one master port and means for interconnection between at least one of the slave ports and at least one of the master ports, the method being characterised in that it comprises the following steps implemented when an access request is routed from a master module connected to a slave port to a slave module connected to a master port: intercepting an item of source information on the link between the master port and the slave module before the slave module receives the request, searching for the item of source information in at least one access control list controlling access to the slave module, blocking the request such that the slave module is unaware of the requested access if the item of source information is not found in the at least one access control list.

Abstract: The invention concerns a bandwidth control method in an on-chip system comprising at least one main master module, at least one secondary master module, at least one slave module and a bus connected to each module on a communication link, the bus comprising interconnection means to make at least one common slave module communicate with at least one main master module and with at least one secondary master module via at least one common path portion, the method comprising the following steps carried out for each common slave module: first detection of a first request to access the common slave module, issued by a main master module, definition of a blocking time Dj associated with the common slave module, blocking, during blocking time Dj, of any data transfer on the at least one common path portion between a secondary master module and the common slave module.

Abstract: The invention concerns a method for monitoring transactions in an on-chip system comprising at least one main master module, at least one secondary master module, at least one slave module and a bus connected to each module, the bus comprising interconnection means to make at least one common slave module communicate with at least one main master module and with at least one secondary master module, the method comprising the following steps implemented during each transaction between a secondary master module and a common slave module: starting a counter upon initial detection of a transaction start signal, waiting for a final detection of a transaction end signal within a predefined time T, closing the transaction if the time tc that has elapsed since starting the counter is greater than predefined time Tmax, and reinitialising the counter.