Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a first channel region and a second channel region that are formed according to at least one of a vertical channel configuration or a dual channel configuration. The first channel region operates as a first channel between a source region and a drain region of the semiconductor arrangement. The second channel region operates as a second channel between the source region and the drain region. A gate region, formed between the first channel region and the second channel region, operates to control the first channel and the second channel. Performance of the semiconductor arrangement is improved, such as an increase in current, because two current paths between the source region and the drain region are provided by the two channels.

Abstract: An apparatus includes coupling and supporting devices for floating and positioning a fixture to dock with another fixture. A coupling device is mounted on the fixture and coupled to an immediate plate using ball bearings to provide movements in X-Y directions as well as angular movements. The supporting device comprises a ball joint mounted between the immediate plate and a supporting plate to allow the fixture to be tilted. Sliding rods and a hinge are mounted on the supporting plate so that the fixture can be flipped over 180 degrees. Springs can be used instead of a ball joint. Sliding tracks and plates can also be used to provide movements in the X-Y directions. Guide devices each having a male guide member with a cone shaped head and a matched female guide member with a cone shaped void are used to guide the fixtures into positions for docking.

Abstract: An automatic tester uses a coarse timing subsystem and a formatter circuit to generate a first formatted waveform with coarse timing based on the information stored in a vector memory subsystem. The first formatted waveform is refined by a timing refiner circuit to form a second formatted waveform with precise timing. The timing refiner circuit includes a flip-flop device to re-synchronize and remove jitter in the first formatted waveform. A counter and/or shift register and vernier circuit in the timing refiner circuit then triggers the leading and trailing edges of the second formatted waveform with precise timing. The formatter circuit may be eliminated by using control signals of the memory devices in the vector memory subsystem to manipulate timing. The coarse timing subsystem may further be eliminated by providing sufficient range for the counters in the timing refiner circuit.

Abstract: A memory testing method for providing test patterns for a memory device is provided. First, the memory is divided into a plurality of blocks and a test pattern is applied to completely test a first block. Next, the first block is filled with all `1`, and other blocks are filled with all `0`. Then, the first block is walked through the entire memory device to quickly test the memory and the function of the address decoder. The invention provides an efficient method for quickly and completely testing the semiconductor memory as well as detecting and locating all the address decoder faults. A method for selecting an optimal number for dividing a memory device into blocks is also presented to minimize the required test time.

Abstract: A set of techniques are disclosed for organizing an electronic memory to increase the effective decoding speed while being able to randomly address storage locations in the memory. The memory typically contains a memory array (41 or 51) and address circuitry (40 or 50). In one memory-organization technique, the address circuitry contains a group of decoding segments (50.sub.1 -50.sub.M) arranged in series. Each decoding segment partially decodes an input memory address. In another memory-organization technique, the address circuitry contains a plurality of decoding segments (40.sub.1 and 40.sub.2) arranged in parallel, each decoding segment sequentially decoding different ones of the input memory addresses than each other decoding segment. A variation of the parallel memory-organization technique can be used with off-the-shelf memories.

Abstract: A method and apparatus for conformance testing of complex entities, such as networks and their protocols. Networks that have their managed objects, attributes and notifications defined in industry standard ASN.1 notation can be methodically processed according to finite state machine models of their managed objects to provide optimum test cases for conformance testing. These test cases are optimum in that they are minimized according to a cost criterion, while designed to test each state of the finite state machine model at least once. A data base stores the optimum test cases of the managed objects to support testing of the defined and modeled network. The method further applies these optimum test cases via a test apparatus to a system-under-test, e.g. a network, to test conformance thereof to its specifications.

Abstract: The present invention relates generally to the fields of molecular biology and the production of recombinant protein using cellular slime moulds of the genus Dictyostelium. Most particularly, the present invention relates to novel strains of the genus Dictyostelium, recombinant plasmids for use with strains of the genus Dictyostelium, and polypeptides which facilitate the extrachromosomal replication of such plasmids in strains of the genus Dictyostelium. In particular, the present invention provides a polypeptide which facilitates the extrachromosomal replication of a recombinant plasmid in Dictyostelium spp in which the recombinant plasmid includes an origin of replication derived from a Ddp2-like plasmid but which lacks functional genes for extrachromosomal replication in wild type Dictyostelium spp.