Patents by Inventor C. Matthew Thompson
C. Matthew Thompson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10090299Abstract: An integrated circuit with transistor regions formed on a substrate. Each transistor region includes a channel region and a terminal region. The channel region is positioned along a traverse dimension, and it includes a channel edge region along a longitudinal dimension. The terminal region is positioned adjacent to the channel region, and it is doped with a first dopant of a first conductivity type. Each transistor region may include an edge block region, which is positioned along the longitudinal dimension and adjacent to the channel edge region. The edge block region is doped with a second dopant of a second conductivity type opposite to the first conductivity type. The channel region doped with a dopant and having a first doping concentration. Each transistor region may include an edge recovery region overlapping with the channel edge region and having a second doping concentration higher than the first doping concentration.Type: GrantFiled: January 9, 2018Date of Patent: October 2, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaoju Wu, C. Matthew Thompson
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Publication number: 20180130798Abstract: An integrated circuit with transistor regions formed on a substrate. Each transistor region includes a channel region and a terminal region. The channel region is positioned along a traverse dimension, and it includes a channel edge region along a longitudinal dimension. The terminal region is positioned adjacent to the channel region, and it is doped with a first dopant of a first conductivity type. Each transistor region may include an edge block region, which is positioned along the longitudinal dimension and adjacent to the channel edge region. The edge block region is doped with a second dopant of a second conductivity type opposite to the first conductivity type. The channel region doped with a dopant and having a first doping concentration. Each transistor region may include an edge recovery region overlapping with the channel edge region and having a second doping concentration higher than the first doping concentration.Type: ApplicationFiled: January 9, 2018Publication date: May 10, 2018Inventors: Xiaoju Wu, C. Matthew Thompson
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Patent number: 9899376Abstract: An integrated circuit with transistor regions formed on a substrate. Each transistor region includes a channel region and a terminal region. The channel region is positioned along a traverse dimension, and it includes a channel edge region along a longitudinal dimension. The terminal region is positioned adjacent to the channel region, and it is doped with a first dopant of a first conductivity type. Each transistor region may include an edge block region, which is positioned along the longitudinal dimension and adjacent to the channel edge region. The edge block region is doped with a second dopant of a second conductivity type opposite to the first conductivity type. The channel region doped with a dopant and having a first doping concentration. Each transistor region may include an edge recovery region overlapping with the channel edge region and having a second doping concentration higher than the first doping concentration.Type: GrantFiled: March 4, 2016Date of Patent: February 20, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaoju Wu, C. Matthew Thompson
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Publication number: 20170256537Abstract: An integrated circuit with transistor regions formed on a substrate. Each transistor region includes a channel region and a terminal region. The channel region is positioned along a traverse dimension, and it includes a channel edge region along a longitudinal dimension. The terminal region is positioned adjacent to the channel region, and it is doped with a first dopant of a first conductivity type. Each transistor region may include an edge block region, which is positioned along the longitudinal dimension and adjacent to the channel edge region. The edge block region is doped with a second dopant of a second conductivity type opposite to the first conductivity type. The channel region doped with a dopant and having a first doping concentration. Each transistor region may include an edge recovery region overlapping with the channel edge region and having a second doping concentration higher than the first doping concentration.Type: ApplicationFiled: March 4, 2016Publication date: September 7, 2017Inventors: Xiaoju Wu, C. Matthew Thompson
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Patent number: 7670920Abstract: An embodiment relates generally to a method of forming a capacitor. The method includes depositing a first layer of polysilicon on a substrate and implanting a high dose of implant into the first layer of polysilicon. The method also includes depositing a layer of dielectric over the first layer of polysilicon and depositing a second layer of polysilicon over the layer of dielectric. The method further includes implanting an equivalent concentration of implant in both the first layer of polysilicon into the second layer of polysilicon.Type: GrantFiled: April 9, 2007Date of Patent: March 2, 2010Assignee: Texas Instruments IncorporatedInventors: Byron Lovell Williams, Maxwell Walthour Lippitt, III, C. Matthew Thompson
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Patent number: 7541275Abstract: The present invention provides an interconnect for use in an integrated circuit, a method for manufacturing the interconnect, and a method for manufacturing an integrated circuit including the interconnect. The interconnect (100), among other elements, includes a surface conductive lead (160) located in an opening formed within a protective overcoat (110), and a barrier layer (140) located between the protective overcoat (110) and the surface conductive lead (160), a portion of the barrier layer (140) forming a skirt (145) that extends outside a footprint of the surface conductive lead (160).Type: GrantFiled: April 21, 2004Date of Patent: June 2, 2009Assignee: Texas Instruments IncorporatedInventors: Betty Shu Mercer, Erika Leigh Shoemaker, Byron Lovell Williams, Laurinda W. Ng, Alec J. Morton, C. Matthew Thompson
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Publication number: 20080246070Abstract: An embodiment relates generally to a method of forming a capacitor. The method includes depositing a first layer of polysilicon on a substrate and implanting a high dose of implant into the first layer of polysilicon. The method also includes depositing a layer of dielectric over the first layer of polysilicon and depositing a second layer of polysilicon over the layer of dielectric. The method further includes implanting an equivalent concentration of implant in both the first layer of polysilicon into the second layer of polysilicon.Type: ApplicationFiled: April 9, 2007Publication date: October 9, 2008Inventors: Byron Lovell Williams, Maxwell Walthour Lippitt, C. Matthew Thompson
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Publication number: 20060199328Abstract: The present invention provides, in one aspect, a method of fabricating a capacitor 615, comprising forming a first electrode 610, placing a dielectric 515 over the first electrode, and locating a second electrode 510 over the dielectric wherein at least one of the first or second electrodes 610, 510 is doped amorphous silicon.Type: ApplicationFiled: March 4, 2005Publication date: September 7, 2006Applicant: Texas Instruments, IncorporatedInventors: Maxwell Lippitt, Byron Williams, Michael DuBois, Betty Mercer, Scott Montgomery, C. Matthew Thompson, Evelyn Lafferty
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Publication number: 20040150065Abstract: In one embodiment of the present invention, a contact structure of a semiconductor device within an integrated circuit includes an active region, the active region having been defined using a mask provided on a substrate. The contact structure further includes an isolation region adjacent the active region and including a field oxide: the field oxide having been grown by exposure of the substrate to a thermal process and an oxygen-containing gas; a film having been formed on a top surface of the mask during exposure to the thermal process and oxygen-containing gas; a dry etching process having been performed to substantially remove the film from the top surface of the mask and to remove a top portion of the field oxide in the isolation region; and a wet etching process having been performed to substantially remove any portion of the mask remaining after the dry etching process.Type: ApplicationFiled: January 20, 2004Publication date: August 5, 2004Inventors: Der-E Jan, Binghua Hu, Betty Shu Mercer, Pushpa Mahalingam, Asadd M. Hosein, John Kenneth Arch, C. Matthew Thompson
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Publication number: 20040007755Abstract: In one embodiment of the present invention, a contact structure of a semiconductor device within an integrated circuit includes an active region, the active region having been defined using a mask provided on a substrate. The contact structure further includes an isolation region adjacent the active region and including a field oxide: the field oxide having been grown by exposure of the substrate to a thermal process and an oxygen-containing gas; a film having been formed on a top surface of the mask during exposure to the thermal process and oxygen-containing gas; a dry etching process having been performed to substantially remove the film from the top surface of the mask and to remove a top portion of the field oxide in the isolation region; and a wet etching process having been performed to substantially remove any portion of the mask remaining after the dry etching process.Type: ApplicationFiled: July 12, 2002Publication date: January 15, 2004Applicant: Texas Instruments IncorporatedInventors: Der-E Jan, Binghua Hu, Betty Shu Mercer, Pushpa Mahalingam, Asadd M. Hosein, John Kenneth Arch, C. Matthew Thompson
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Patent number: 6284669Abstract: A power field effect transistor is disclosed that includes polysilicon gate bodies (40) and (42), which includes platinum silicide contact layers (74) and (78) disposed on the outer surfaces of bodies (40) and (42), respectively. In addition, the device comprises an n+drain region (64) which also has a platinum silicide drain contact layer (76) formed on its outer surface and platinum silicide source contact layers (75) and (77). During formation, sidewall spacers (50) and (52), as well as mask bodies (70) and (72) are used to ensure that platinum silicide layer (76) spaced apart from both gate bodies (40) and (42) and platinum silicide gate contact layers (74) and (78).Type: GrantFiled: October 7, 1998Date of Patent: September 4, 2001Assignee: Texas Instruments IncorporatedInventors: John P. Erdeljac, Louis N. Hutter, Jeffrey P. Smith, Han-Tzong Yuan, Jau-Yuann Yang, Taylor R. Efland, C. Matthew Thompson, John K. Arch, Mary Ann Murphy