Abstract: A process for fabricating integrated injection logic structures including both vertical and lateral bipolar transistors in oxide isolated pockets of silicon includes the steps of forming a patterned composite silicon nitride-silicon dioxide layer to serve as a transistor emitter and self-aligned base mask, and introducing desired impurities to form the lateral transistor emitter and collector. The mask is partially removed and additional impurities introduced to form the vertical transistor base and vertical transistor collector.The process does not require the use of vapor deposited silicon dioxide to pattern the wafer surface, and therefore reduces pinhole defects and the encroachment of the field oxidation on the epitaxial silicon pocket in which devices are formed. The process also results in a flatter topography to allow more uniform and reliable metal interconnections.