Abstract: A fiber-based reflective lighting device and a housed lighting device. The fiber-based reflective lighting device which includes a source configured to generate a primary light, and a substrate having a nanocomposite mat of reflective fibers having a diameter less than 1,000 nm which diffusively reflects light upon illumination with at least the primary light. The nanocomposite mat includes a reflectance-enhancing coating conformally disposed around an outer surface of the fibers, having a refractive index different from the reflective fibers, and which increases a reflectance of the substrate in the visible spectrum. The lighting device includes a light exit configured to emanate the reflected light. The housed lighting device includes a housing, a source configured to generate primary light and direct the primary light into the housing, the reflective nanocomposite mat of reflective fibers, and a light exit in the housing configured to emanate the reflected light from the housing.

Abstract: Techniques are disclosed for performing an auxiliary operation via a compute engine associated with a host computing device. The method includes determining that the auxiliary operation is directed to the compute engine, and determining that the auxiliary operation is associated with a first context comprising a first set of state parameters. The method further includes determining a first subset of state parameters related to the auxiliary operation based on the first set of state parameters. The method further includes transmitting the first subset of state parameters to the compute engine, and transmitting the auxiliary operation to the compute engine. One advantage of the disclosed technique is that surface area and power consumption are reduced within the processor by utilizing copy engines that have no context switching capability.

Abstract: A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.

Abstract: The present invention is directed to systems and methods for establishing incident communications networks. In an embodiment, the system includes an incident controller, a communications resource database that stores communications resources information and a marshalling rules module that stores a set of marshalling rules. A marshalling rule identifies how to select the communications resources to be marshaled into the incident communications network based on an incident trigger. Upon receipt of an incident trigger, the incident controller is configured to establish the incident communications network by obtaining a marshalling rule based on the incident trigger. The incident controller marshals communications resources based on the marshalling rule and the communications resources determined to be available. Information sources can either provide an incident trigger (e.g., a hurricane warning) or provide data to be analyzed to determine an incident trigger.

Abstract: An embodiment of a computing system is configured to process data using a multithreaded SIMD architecture that includes heterogeneous processing engines to execute a program. The program is constructed of various program instructions. A first type of the program instructions can only be executed by a first type of processing engine and a third type of program instructions can only be executed by a second type of processing engine. A second type of program instructions can be executed by the first and the second type of processing engines. An assignment unit may be configured to dynamically determine which of the two processing engines executes any program instructions of the second type in order to balance the workload between the heterogeneous processing engines.

Abstract: A photoluminescent nanofiber composite includes a nanofiber substrate, first luminescent particles, and second luminescent particles. The first luminescent particles are supported by the nanofibers and span at least a portion of a substrate surface, as a layer on the substrate surface, or with some particles located in a bulk of the substrate, or both. The second luminescent particles are disposed on the substrate. The second luminescent particles may be disposed directly on the substrate surface or on the first luminescent particles. The second luminescent particles may be deposited in a pattern of deposition units. The first and second luminescent particles are configured for emitting light of different respective wavelengths in response to excitation by a light beam. One or more surface treatment coatings may be provided at different locations.

Abstract: A processor, memory, first transceiver, second transceiver, plurality of wired and wireless ports, and a power system storing excess energy are provided. Multiple similar systems may mesh communication via first transceiver. Unencrypted data from ports are packaged into unencrypted data structures and forwarded to the second transceiver for transmission according to the telecommunications standard of the second transceiver. A method may include determining if either a predefined time to sample data was reached or if an interrupt was received, and then sampling ports associated with the predefined time or interrupt, to collect data from remote sensors or equipment coupled to the ports, process the sampled data, store the processed data in memory, and evaluate the stored data against a set of rules. If no rules are violated, the sampling continues, and the processed data is packaged and transmitted to a server at a prescheduled time. Actions are taken if rules are violated.

Abstract: A system and method for locking and unlocking access to a shared memory for atomic operations provides immediate feedback indicating whether or not the lock was successful. Read data is returned to the requestor with the lock status. The lock status may be changed concurrently when locking during a read or unlocking during a write. Therefore, it is not necessary to check the lock status as a separate transaction prior to or during a read-modify-write operation. Additionally, a lock or unlock may be explicitly specified for each atomic memory operation. Therefore, lock operations are not performed for operations that do not modify the contents of a memory location.

Abstract: A subterranean tool that is self contained for actuation can be run into a desired location on an automatic set mode controlled by a timer. If a problem develops in getting the tool to the desired location in time a magnetic field created by permanent or electro-magnets can be brought to bear on the tool to stop the timer before the tool actuates. Once the tool is subsequently positioned at the desired location another magnetic field can be brought to bear near the tool to set it. Alternatively, the tool can be run to the desired location without activation with the timer and then the magnetic field can be brought to the tool to set it. The magnetic field can be lowered to the tool with wireline or can be dropped or pumped past the tool to actuate the tool. Optionally the field can be generated from within an object that ultimately lands on a seat to provide a backup way to set the tool using tubing pressure.

Abstract: Pressure relief devices comprise a chamber having a piston disposed therein. One side of the piston defines a hydrostatic chamber in fluid communication with an outside environment, such as an isolated wellbore annulus, through a port. The other side of the piston defines a sealed or isolated chamber. The pressure relief device permits changes in pressure in the isolated wellbore annulus to be distributed into the chambers so as to either reduce the pressure within the isolated wellbore annulus or increase the pressure within the wellbore annulus, both of which lessen the likelihood that the change in pressure within the isolated wellbore annulus will damage wellbore components disposed therein.

Abstract: The present invention is directed to a system and method for providing an interoperable communications system including a plurality of otherwise disjunct communication systems each including at least one communications device. The system includes a plurality of system interface controllers each coupled to one of the communication systems and a common network for connecting the communication system and associated communications devices to the common network. A controller is coupled to each of the system interface controllers. The system interface controller being operable in response to commands from an authorized controller wherein the connection between each of the communication systems and the common network is controlled by a controller associated with, and authorized to control each communication system.

Abstract: An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches.

Abstract: One embodiment of the present invention sets forth a technique for efficiently performing voting operations within a multi-threaded parallel-processing system. A group of related parallel program threads executes within a processor core together in parallel. A new instruction, called a “vote” instruction, is introduced that enables a parallel program thread to post an individual vote within the context of the group of related threads and to receive the result of the vote. In this fashion, the vote instruction advantageously reduces overhead associated with inter-thread communication, thereby improving overall system performance.

Abstract: A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.

Abstract: An actuator and method for setting a subterranean tool uses an externally mounted actuator on a tubular string that is operably engaged to the tool to be actuated. At the desired location for actuation a signal is given to a valve assembly. The opening of the valve releases the pressurized compressible fluid against a floating piston. The piston drives viscous fluid ahead of itself through the now open valve that in turn drives an actuating piston whose movement sets the tool. The triggering mechanism to open the valve can be a variety of methods including an acoustic signal, a vibration signal, a change in magnetic field, or elastic deformation of the tubular wall adjacent the valve assembly.

Abstract: A scoreboard memory for a processing unit has separate memory regions allocated to each of the multiple threads to be processed. For each thread, the scoreboard memory stores register identifiers of registers that have pending writes. When an instruction is added to an instruction buffer, the register identifiers of the registers specified in the instruction are compared with the register identifiers stored in the scoreboard memory for that instruction's thread, and a multi-bit value representing the comparison result is generated. The multi-bit value is stored with the instruction in the instruction buffer and may be updated as instructions belonging to the same thread complete their execution. Before the instruction is issued for execution, this multi-bit value is checked. If this multi-bit value indicates that none of the registers specified in the instruction have pending writes, the instruction is allowed to issue for execution.

Abstract: A fuel additive is disclosed which comprises a suspension of nanoparticle oxides in a fuel miscible liquid carrier, which suspension may be colloidal or otherwise. Methods for enhancing combustion and fuel economy and reducing emissions by employing said fuel additive are also disclosed.

Abstract: A hydraulic circuit (88) for an automatic transmission (10) that employs a shift actuation valve (96) that controls the actuation of the synchronizer (29) for selectively controlling gear engagement. The shift actuation valve (96) includes a valve member (114) having at least one valve element (122) with an outer diameter (162) and a metering face (164). The metering face (164) is adapted to control the flow of pressurized fluid between an inlet (108) and an outlet (110) of the valve body (102). The metering face (164) includes a flow force compensating annular void (166) disposed adjacent the outer diameter (162) and that is defined by a lead angle ? measured between the outer diameter (162) and a line intersecting the outer diameter (162) and tangential to the annular void (166). A solenoid (104) is employed to move the valve member (114) between predetermined positions.