Abstract: A digital system has a resource, such as a communication bus, adapted for access by a plurality of devices, a plurality of devices adapted to access the resource, and an arbitrator for arbitrating access to the resource by the devices. The arbitrator includes a programmable memory comprising a plurality of addressable words and an address generator for cyclically sequentially addressing each of the memory words. Each word stores information defining a priority order of the devices for accessing the resource. In particular, each word is divided into a plurality of segments, and each segment corresponds with a priority level in the order of priority. Each segment holds information identifying the device currently having the corresponding priority level. The priority order is changeable by reprogramming the contents of the memory. The priority order so implemented may be any conceivable order, and in particular may include a constant decreasing priority, a round-robin priority, or a combination of the two.