Abstract: A field selection data operating device consists of three cascade connected circuits: a field selector and shifter circuit, an arithmetical and logical operator circuit and a bit shifter and concatenator circuit. The selector and shifter circuit is controlled by a field length code, a shift value code and a first field bit rank code. It comprises two stages of multiplexing members. The first stage ensures, in circular permutation, a shift of the bytes of an applied data word so as to place the byte containing the bit of the first field bit rank code at the place in the word pointed by the shift value code and the second stage completes the shift to the said bit in the byte and generates an output mask according to the field length code. The mask is also applied to concatenation control inputs of the bit shifter and concatenator circuit.