Patents by Inventor C. R. Hsu

C. R. Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9318504
    Abstract: One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of cells is associated with a dummy region. For example, the array of cells includes an array of gates and an array of OD regions. In some embodiments, the array of gates includes a first set of gates associated with a first gate dimension and a second set of gates associated with a second gate dimension. In some embodiments, the array of OD regions includes a first set of OD regions associated with a first OD dimension and a second set of OD regions associated with a second OD dimension. In this manner, at least one of a pattern density, gate density, or OD density is customized to a region associated with active cells, thus mitigating density gradients between respective regions.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: April 19, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yu-Jung Chang, C. R. Hsu, Chin-Chang Hsu, Wen-Ju Yang, Chung-min Fu
  • Publication number: 20160020222
    Abstract: One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of cells is associated with a dummy region. For example, the array of cells includes an array of gates and an array of OD regions. In some embodiments, the array of gates includes a first set of gates associated with a first gate dimension and a second set of gates associated with a second gate dimension. In some embodiments, the array of OD regions includes a first set of OD regions associated with a first OD dimension and a second set of OD regions associated with a second OD dimension. In this manner, at least one of a pattern density, gate density, or OD density is customized to a region associated with active cells, thus mitigating density gradients between respective regions.
    Type: Application
    Filed: September 28, 2015
    Publication date: January 21, 2016
    Inventors: Yu-Jung Chang, C.R. Hsu, Chin-Chang Hsu, Wen-Ju Yang, Chung-min Fu
  • Patent number: 9147694
    Abstract: One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of cells is associated with a dummy region. For example, the array of cells includes an array of gates and an array of OD regions. In some embodiments, the array of gates includes a first set of gates associated with a first gate dimension and a second set of gates associated with a second gate dimension. In some embodiments, the array of OD regions includes a first set of OD regions associated with a first OD dimension and a second set of OD regions associated with a second OD dimension. In this manner, at least one of a pattern density, gate density, or OD density is customized to a region associated with active cells, thus mitigating density gradients between respective regions.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: September 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Jung Chang, C. R. Hsu, Chin-Chang Hsu, Wen-Ju Yang, Chung-min Fu
  • Patent number: 8751978
    Abstract: Among other things, one or more techniques for balancing mask loading are provided herein. In some embodiments, a dummy mask assignment is assigned to a dummy within a mask layout based on an area of a polygon within the mask layout. In some embodiments, the dummy mask comprising the dummy mask assignment is inserted in the mask layout. In some embodiments, a window is created such that dummies within the window receive dummy mask assignments. In some embodiments, a halo is created such that the area of the polygon is determined based on the halo. Additionally, in some examples, the window and halo are shifted around the mask layout. In this manner, balanced mask loading is provided, thus enhancing a yield associated with the mask layout, for example.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: HungLung Lin, Chin-Chang Hsu, Wen-Ju Yang, C. R. Hsu