Abstract: A damping circuit is described which includes a phase-and-frequency detector, a charge pump, a voltage-current oscillator and a capacitor. The phase-and-frequency detector generates UP and DOWN signals representative of a difference in phase between a pair of digital input signals. The charge pump varies an amount of charge carried within the capacitor in accordance with the UP and DOWN signals. The voltage controlled oscillator generates an output signal having a frequency controlled by both a voltage provided by the capacitor and by the UP and DOWN signals directly received from the phase-and-frequency detector. No analog damping resistor is required. Rather, the damping circuit is an digital circuit which generates adequate phase and frequency damping without a damping resistor. Damping is achieved which is substantially unaffected by process parameters and operating and ambient parameters. Method embodiments of the invention are also described.

Abstract: A package for an integrated circuit is described. The package houses an integrated circuit with a signal quality sensitive integrated circuit element, such as a voltage controlled oscillator of a phase-locked loop. A package-mounted storage capacitor is positioned on the package body to generate a precision control signal. A signal path is constructed between the package-mounted storage capacitor and the integrated circuit to route the precision control signal to the integrated circuit. The relatively short signal path from the package-mounted storage capacitor to the integrated circuit has reduced parasitic capacitance, inductance, and resistance to maintain the quality of the precision control signal. To improve signal quality, certain portions of the signal path are electrically isolated with a shielding trace.

Abstract: A reset circuit for a phase detector in a phase-locked loop is described. A first set of input lines receives a first set of latched signals corresponding to a cycle of a reference signal applied to the phase detector of the phase-locked loop. Reset assertion logic is connected to the first set of input lines and executes a predetermined logic function on the first set of latched signals to generate a reset signal that is applied to an output node. The generated reset signal has a cycle duration corresponding to the reference signal cycle duration. Reset de-assertion logic is connected to the first set of input lines and executes a predetermined logic function on the first set of latched signals to de-assert the generated reset signal after a period of time corresponding to the reference signal cycle duration. Similar processing may be performed in relation to a second set of latched signals corresponding to a cycle of a feedback signal applied to the phase detector of the phase-locked loop.

Abstract: A charge pump circuit contains a first switch pass gate, a second switch pass gate, a high node regulator, and a low node regulator. The first switch pass gate couples a high node to a charge pump output when an up control signal is active, and the second switch pass gate couples a low node to the charge pump output when a down control signal is active. The high node regulator receives the charge pump output and a source voltage for the charge pump circuit, and generates a high node voltage at the high node such that the high node voltage is regulated to a voltage above a predetermined margin of the charge pump output. The low node regulator is coupled to ground, and receives the charge pump output to generate a low node voltage at the low node that is regulated to a voltage below a predetermined margin of the charge pump output. The charge pump circuit has application for use in a phase lock loop.

Abstract: A method and apparatus for implementing a zero latency synchronizer that permits the reliable transfer of data between clock domains by placing a metastability delay in the clock path. The zero latency synchronizer for synchronizing a signal from a first clock domain to a second clock domain is formed from a clock regenerator circuit and input and output master slave flip flops. The clock regenerator receives a first clock from the first clock domain and a second clock from the second clock domain and generates first and second regenerated clock signals. The first and second regenerated clock signals are formed in a manner that guarantees that the first and second regenerated clocks, in conjunction with the first and second clocks, can be used to control the input and output master slave flip flops and thereby pass data reliably from one clock domain to the other without delay.

Abstract: A range finding device and method for determining the distance between a merged submarine and a target above the surface having a first and second periscopes mounted on a submarine with a known separation. These periscopes are rotatable and extensible above the surface and can determine the bearing from each of the periscopes to the target. A computer receives the bearings from the first and second periscopes and uses the bearings with the known preset distance between the periscopes to calculate the distance between the submarine and the target.

Abstract: An integrated circuit includes a bipolar logic stage and a CMOS logic stage. The bipolar logic stage includes a common emitter line positioned along a central axis, and a set of bipolar signal drive blocks arranged along the central axis. Each of the bipolar signal drive blocks includes a bipolar transistor with an emitter connected to the common emitter line. Each of the bipolar signal drive blocks further includes an emitter-base reverse voltage protection device. The CMOS logic stage includes a plurality of CMOS logic blocks connected to the set of bipolar signal drive blocks. The CMOS logic blocks are arranged in a compact configuration that is substantially perpendicular to the central axis. The CMOS logic stage performs logical operations on a set of input signals to generate a set of intermediate signals that are driven by the set of bipolar signal drive blocks onto the common emitter line.

Abstract: A vocal communication snorkel includes a hollow body having a breather tube, adapted to extend above the water, coupled thereto and a mouthpiece adapted to be held by the lips of a snorkeler. The body has a pair of inwardly curved, spherically shaped diaphragms of thin plastic material that are tuned to resonance within the frequency band of 1500 to 3000 Hertz in water. The mouthpiece includes a passageway that is coupled to the body and a pair of flexible lips, that are closable by the lips of the snorkeler for articulating plosive sounds. A readily collapsible bubble, formed in the passageway and engageable by the lower lip of the snorkeler, facilitates closure of the passageway under pressure from the snorkeler's lower lip.

Abstract: A hammer having a plastic molded handle. The rear end of the handle has a longitudinally extending bore hole that is filled with a gelatinous material that dissipates shock vibrations. An end cap is secured to the rear end of the handle by sonic welding. The front end of the handle has both a vertical and a horizontal longitudinally extending slot and these slots intersect each other at a substantially 90 degree angle. A plastic wedge unit formed from intersecting wedge sections is driven into the slots in the top end of the handle to secure the hammer head and the wedge unit is sonic welded to the handle.

Abstract: A high speed processing flip-flop contains a header circuit and a pulse flip-flop circuit. The header circuit is a clock pre-processing circuit that generates clock pulses for operation of the pulse flip-flop circuit, and the pulse flip-flop circuit is a single stage latch. The header circuit contains functional logic including the flip-flop functionality for the high speed processing flip-flop, and any additional processing functions, such as multiplexing. The header circuit also contains a pulse modulator that generates selected clock pulses, based on the functional logic, for the pulse flip-flop circuit. The pulse flip-flop circuit contains storage, a driver circuit, and, for each data input, an input buffer, and a pass gate. The pulse flip-flop circuit couples the data to the driver circuit and storage during an active clock pulse for the corresponding data. Consequently, data input to the pulse flip-flop is not delayed by logic processing.

Abstract: The complementary multiplexer includes a first pass-gate, formed from a single PMOS transistor, and a second pass-gate formed from a single NMOS transistor. The gates of the PMOS and NMOS transistors are connected directly to a select input line. No inversion of the select input signal is required. A compensation circuit is connected to outputs of the pass-gates for compensating any voltage differences between signals received through the first pass-gate as opposed to those received through the second pass-gate. Full CMOS and bi-CMOS implementations are described herein. An exclusive OR-gate circuit, incorporating a bi-CMOS implementation of the multiplexer, is also described herein.

Abstract: A damping circuit is described which includes a phase-and-frequency detector, a charge pump, a voltage-current oscillator and a capacitor. The phase-and-frequency detector generates UP and DOWN signals representative of a difference in phase between a pair of digital input signals. The charge pump varies an amount of charge carried within the capacitor in accordance with the UP and DOWN signals. The voltage controlled oscillator generates an output signal having a frequency controlled by both a voltage provided by the capacitor and by the UP and DOWN signals directly received from the phase-and-frequency detector. No analog damping resistor is required. Rather, the digital damping circuit is a digital circuit which generates adequate phase and frequency damping without a damping resistor. In this manner damping is achieved which is substantially unaffected by process parameters and operating and ambient parameters. Method embodiments of the invention are also described.

Abstract: A microphone for use in a harsh environment of intense vibration and sound pressure. A microphone transducer and an acceleration transducer are located adjacent each other inside of a housing. The microphone transducer substantially blocks much of the acoustic signal from reaching the acceleration transducer. Accordingly, the acceleration transducer provides a signal substantially related only to the movement of the microphone, while the microphone transducer provides a signal related to both the movement of the microphone and the acoustic signal applied to it. The acceleration signal may then be removed from the microphone signal, providing a electrical signal substantially representative only of the acoustic signal.

Abstract: A high speed, low powered, BiCMOS TTL to CMOS translator circuit and method which relies on an internally generated reference voltage and which is capable of driving high loads. The translator circuit includes a first inverting and translating stage having a pull up transistor and a pull down transistor, a high gain stage and a second inverting stage.

Abstract: A reclining chair is provided with an ottoman (or leg rest) which includes primary (or main) and secondary (or mid or middle) ottoman members separately mounted to pantographic linkage subsystems of the side linkages of the chair-operating mechanism. Both ottoman members are padded and include side skirts for veiling respective portions of the side linkages when the ottoman is in a raised condition. The secondary ottoman is articulated directly to the primary ottoman, for control, so that as the ottoman is being retracted to a stowed position below the front of the seat, the secondary ottoman is rotated from a face-upwards, to a face-rearwards orientation, and received into a pocket formed behind the primary ottoman, which is rotated from a face-upwards, to a face-forwards orientation.

Abstract: Typically, a disc brake the caliper assembly is mounted by a pair of specially configured mounting bolts to a cast-iron steering knuckle. In many models, the bolts are threadingly engaged with a steering knuckle or similar support structure in order to retain the bolts in place. To remove the caliper assembly, the two caliper mounting bolts are removed. However, in many instances, during servicing of the disc brakes, the threads within one of the apertures defined in the steering knuckle become stripped. A caliper mounting replacement bolt is provided having oversized self-tapping threads and an associated aperture for auxiliary retention. The inventive replacement bolt is used in place of the original caliper mounting bolt to enable reinstallation of the brake caliper assembly onto the steering knuckle in a quick and efficient manner. During the installation thereof, the inventive mounting bolt cuts a new thread into the steering knuckle aperture.

Abstract: A test strip for measuring film build on a plastic piece includes a desired length of tape having an adhesive coating on an inner surface and a window. A paint strip of sufficient area to cover the window is secured to the tape by the adhesive. A backing formed from material easily peeled from the adhesive is removed when the tape is mounted on a piece prior to painting. After painting, the test strip is peeled away from the piece so that the paint strip can be separated from the tape, analyzed and stored.

Abstract: One-piece garter spring coupling release tool. The release tool is molded in a single selectively configured shape out of a durable, flexible plastic material such as Elastollan.TM. S98A available from Elastogran of Germany. The release tool generally comprises a cylindrical body with a slot along its length and a flange on one end. The slot permits the tool to be positioned around a port to which a garter spring coupling is connected; the flange provides an area for gripping the tool to releasably engage the tool with its coupling. The flexible, slotted configuration of the garter spring coupling release tool permits nesting of a four-piece set of such tools within each other to facilitate packaging, storage and retention of the tools as a set.

Abstract: A housing having a cavity is arranged for mounting within a cabinet structure, with the apparatus to include a first drive motor to effect selective rotation in a clockwise and counter-clockwise manner to permit the selective closure and removal of jar lids relative to an associated jar employing threaded interconnection, with a second motor arranged for operative and selective actuation of a can opening device.

Abstract: A voltage interfacing buffer for interfacing a low voltage integrated circuit to a high voltage environment, wherein the integrated circuit contains only low voltage transistors. To drive the high voltage environment at the low voltage swing, the voltage interfacing circuit employs protection circuits and novel n-well biasing of MOS transistors. To drive the high voltage environment at the high voltage swing, the voltage interfacing circuit employs a bias generator circuit to bias buffer transistors supplied with the high voltage. As example applications, the voltage interfacing buffer enables a 3 volt or 3.3 volt integrated circuit chip to drive TTL as well as CMOS voltage levels. Moreover, the voltage interfacing buffer enables a 2 volt integrated circuit chip to drive TTL voltage levels.