Patents by Inventor C. Scott Huddleston

C. Scott Huddleston has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Enhanced storage of metadata utilizing improved error detection and correction in computer memory
    Patent number: 9195551
    Abstract: A novel ECC scheme is disclosed that offers an error protection level that is at least the same as (if not better than) that of the conventional ECC scheme without negatively impacting latency and design complexity. Embodiments of the present disclosure utilize an ECC scheme which leaves up to extra 2B for metadata storage by changing the error detection and correction process flow. The scheme adopts an early error detection mechanism, and tailors the need for subsequent error correction based on the results of the early detection.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: November 24, 2015
    Assignee: INTEL CORPORATION
    Inventors: Debaleena Das, Rajat Agarwal, C. Scott Huddleston
  • ENHANCED STORAGE OF METADATA UTILIZING IMPROVED ERROR DETECTION AND CORRECTION IN COMPUTER MEMORY
    Publication number: 20140047265
    Abstract: A novel ECC scheme is disclosed that offers an error protection level that is at least the same as (if not better than) that of the conventional ECC scheme without negatively impacting latency and design complexity. Embodiments of the present disclosure utilize an ECC scheme which leaves up to extra 2B for metadata storage by changing the error detection and correction process flow. The scheme adopts an early error detection mechanism, and tailors the need for subsequent error correction based on the results of the early detection.
    Type: Application
    Filed: March 29, 2012
    Publication date: February 13, 2014
    Inventors: Debaleena Das, Rajat Agarwal, C. Scott Huddleston
  • Mechanisms and techniques for providing cache tags in dynamic random access memory
    Patent number: 8612832
    Abstract: A dynamic random access memory (DRAM) is operated as a cache memory coupled with a processor core. A block of data is transmitted to the DRAM as even and odd pairs of bits from the processor core. The block of data includes N error correcting code (ECC) bits and 11*N data bits. Two or more cache lines are to be stored in a memory page with tag bits aggregated together within the page.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: December 17, 2013
    Assignee: Intel Corporation
    Inventors: Darrell S. McGinnis, C. Scott Huddleston, Rajat Agarwal, Meenakshisundaram R. Chinthamani
  • MECHANISMS AND TECHNIQUES FOR PROVIDING CACHE TAGS IN DYNAMIC RANDOM ACCESS MEMORY
    Publication number: 20120254700
    Abstract: A dynamic random access memory (DRAM) is operated as a cache memory coupled with a processor core. A block of data is transmitted to the DRAM as even and odd pairs of bits from the processor core. The block of data includes N error correcting code (ECC) bits and 11*N data bits. Two or more cache lines are to be stored in a memory page with tag bits aggregated together within the page.
    Type: Application
    Filed: April 1, 2011
    Publication date: October 4, 2012
    Inventors: Darrell S. McGinnis, C. Scott Huddleston, Rajat Agarwal, Meenakshisundara R. Chinthamani
  • Data line storage and transmission utilizing both error correcting code and synchronization information
    Patent number: 8239737
    Abstract: Methods and apparatuses for including synchronization data to be used for parallel processing in a block of data having error correcting code symbols. The block of data is encoded using an error correcting code. The resulting encoding includes three check symbols per 32 data symbols. At least one synchronization symbol corresponding to the data symbols is generated. The data symbols, the check symbols and the at least one synchronization symbol are combined. The combined data symbols, the check symbols and the at least one synchronization symbol are transmitted.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: August 7, 2012
    Assignee: Intel Corporation
    Inventors: Rajat Agarwal, C. Scott Huddleston
  • DATA LINE STORAGE AND TRANSMISSION UTILIZING BOTH ERROR CORRECTING CODE AND SYNCHRONIZATION INFORMATION
    Publication number: 20110145678
    Abstract: Methods and apparatuses for including synchronization data to be used for parallel processing in a block of data having error correcting code symbols. The block of data is encoded using an error correcting code. The resulting encoding includes three check symbols per 32 data symbols. At least one synchronization symbol corresponding to the data symbols is generated. The data symbols, the check symbols and the at least one synchronization symbol are combined. The combined data symbols, the check symbols and the at least one synchronization symbol are transmitted.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 16, 2011
    Inventors: Rajat Agarwal, C. Scott Huddleston