Abstract: Apparatuses and methods associated with shaping codes for memory are provided. One example apparatus comprises an array of memory cells and a shaping component coupled to the array and configured to encode each of a number of received digit patterns according to a mapping of received digit patterns to shaping digit patterns. The mapping of received digit patterns to shaping digit patterns obeys a shaping constraint that limits, to an uppermost amount, an amount of consecutive digits of the shaping digit patterns allowed to have a particular digit value.

Abstract: Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (RTSs), and determining log-likelihood-ratios (LLRs) based on a number of decisions that correspond to each bin associated with the selected RTSs. Low-density parity-check (LDPC) codewords are decoded using the determined LLRs, and a RTS of the RTSs yielding a least number of failed codewords decoded using the determined LLRs is identified.

Abstract: The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes mapping a data pattern to a number of program state combinations L corresponding to a group of memory cells configured to store a fractional number of data units per cell. The mapping can be based, at least partially, on a recursive expression performed in a number of operations, the number of operations based on a number of memory cells N within the group of memory cells and the number of program state combinations L.

Abstract: Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (RTSs), and determining log-likelihood-ratios (LLRs) based on a number of decisions that correspond to each bin associated with the selected RTSs. Low-density parity-check (LDPC) codewords are decoded using the determined LLRs, and a RTS of the RTSs yielding a least number of failed codewords decoded using the determined LLRs is identified.

Abstract: The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes mapping a data pattern to a number of program state combinations L corresponding to a group of memory cells configured to store a fractional number of data units per cell. The mapping can be based, at least partially, on a recursive expression performed in a number of operations, the number of operations based on a number of memory cells N within the group of memory cells and the number of program state combinations L.

Abstract: A memory device may include memory components for storing data. The memory device may also include a controller that determines whether one or more errors exist in a data packet stored in the memory components. The controller may read a code word associated with the data packet, such that the code word may be used to indicate whether the errors exist in the data packet. The controller may then determine a syndrome polynomial based on the code word and determine an inverse of the syndrome polynomial when the syndrome polynomial is not zero. The controller may then determine a first error locator polynomial and a second error locator polynomial based on the inverse of the syndrome polynomial. The first error locator polynomial and the second error locator polynomial may be used to identify one or more locations of one or more errors in the code word.

Abstract: Methods and apparatuses for combining error coding and modulation schemes are described herein. One or more methods include encoding data using linear error correcting code, modulating the encoded data, writing the modulated data to memory, and decoding the written data using a Viterbi algorithm and a linear error correcting code decoder.

Abstract: Apparatuses and methods for resolving trapping sets are provided. One example method can include attempting to decode a codeword using initial values for confidence levels associated with digits of the codeword. For a trapping set, the confidence levels associated with the digits corresponding to a failed parity check are adjusted. The method further includes attempting to decode a codeword using the adjusted value for the confidence levels of the digits corresponding to the failed parity check.

Abstract: Methods of operating an apparatus such as a computing system and/or memory device for memory endurance are provided. One example method can include receiving m digits of data having a first quantity of digits represented by a first data state that is more detrimental to memory cell wear than a second data state. The m digits of data are encoded into n digits of data having a second quantity of digits represented by the first data state. The value n is greater than the value m. The second quantity is less than or equal to the first quantity. The n digits of data are stored in an apparatus having memory cells.

Abstract: Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (RTSs), and determining log-likelihood-ratios (LLRs) based on a number of decisions that correspond to each bin associated with the selected RTSs. Low-density parity-check (LDPC) codewords are decoded using the determined LLRs, and a RTS of the RTSs yielding a least number of failed codewords decoded using the determined LLRs is identified.

Abstract: Apparatuses and methods associated with shaping codes for memory are provided. One example apparatus comprises an array of memory cells and a shaping component coupled to the array and configured to encode each of a number of received digit patterns according to a mapping of received digit patterns to shaping digit patterns. The mapping of received digit patterns to shaping digit patterns obeys a shaping constraint that limits, to an uppermost amount, an amount of consecutive digits of the shaping digit patterns allowed to have a particular digit value.

Abstract: The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes mapping a data pattern to a number of program state combinations L corresponding to a group of memory cells configured to store a fractional number of data units per cell. The mapping can be based, at least partially, on a recursive expression performed in a number of operations, the number of operations based on a number of memory cells N within the group of memory cells and the number of program state combinations L.

Abstract: Methods for programming memory cells. One such method for programming memory cells includes generating an encoded stream using a data stream and programming the memory cells using the encoded stream to represent the data stream. A particular bit position of the encoded stream has a first voltage level when the particular bit position of the data stream has a particular logical state, and the particular bit position of the encoded stream has either a second voltage level or a third voltage level when the particular bit position of the data stream has a logical state other than the particular logical state.

Abstract: Apparatuses and methods associated with shaping codes for memory are provided. One example apparatus comprises an array of memory cells and a shaping component coupled to the array and configured to encode each of a number of received digit patterns according to a mapping of received digit patterns to shaping digit patterns. The mapping of received digit patterns to shaping digit patterns obeys a shaping constraint that limits, to an uppermost amount, an amount of consecutive digits of the shaping digit patterns allowed to have a particular digit value.

Abstract: Methods and apparatuses for combining error coding and modulation schemes are described herein. One or more methods include encoding data using linear error correcting code, modulating the encoded data, writing the modulated data to memory, and decoding the written data using a Viterbi algorithm and a linear error correcting code decoder.

Abstract: Some embodiments include apparatus and methods for encoding message information. Such apparatus and methods can include using a parity check matrix of a low-density parity check (LDPC) code to generate a first matrix having an upper triangular sub-matrix. Parity information to encode the message information can be generated based on the first matrix if a total number of rows of the upper triangular sub-matrix is equal to the rank of the parity check matrix. If the total number of rows of the upper triangular sub-matrix is less than the rank of the parity check matrix, then a triangularization operation can be performed on a second sub-matrix of the first matrix to generate a second matrix. Parity information to encode the message information can be generated based on the second matrix. Other embodiments including additional apparatus and methods are described.

Abstract: Methods and apparatuses for combining error coding and modulation schemes are described herein. One or more methods include encoding data using linear error correcting code, modulating the encoded data, writing the modulated data to memory, and decoding the written data using a Viterbi algorithm and a linear error correcting code decoder.

Abstract: Methods of operating an apparatus such as a computing system and/or memory device for memory endurance are provided. One example method can include receiving m digits of data having a first quantity of digits represented by a first data state that is more detrimental to memory cell wear than a second data state. The m digits of data are encoded into n digits of data having a second quantity of digits represented by the first data state. The value n is greater than the value m. The second quantity is less than or equal to the first quantity. The n digits of data are stored in an apparatus having memory cells.

Abstract: Methods for programming memory cells. One such method for programming memory cells includes generating an encoded stream using a data stream and programming the memory cells using the encoded stream to represent the data stream. A particular bit position of the encoded stream has a first voltage level when the particular bit position of the data stream has a particular logical state, and the particular bit position of the encoded stream has either a second voltage level or a third voltage level when the particular bit position of the data stream has a logical state other than the particular logical state.

Abstract: Some embodiments include apparatus and methods for encoding message information. Such apparatus and methods can include using a parity check matrix of a low-density parity check (LDPC) code to generate a first matrix having an upper triangular sub-matrix. Parity information to encode the message information can be generated based on the first matrix if a total number of rows of the upper triangular sub-matrix is equal to the rank of the parity check matrix. If the total number of rows of the upper triangular sub-matrix is less than the rank of the parity check matrix, then a triangularization operation can be performed on a second sub-matrix of the first matrix to generate a second matrix. Parity information to encode the message information can be generated based on the second matrix. Other embodiments including additional apparatus and methods are described.