Patents by Inventor Cadence Design Systems, Inc.

Cadence Design Systems, Inc. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130191793
    Abstract: A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment.
    Type: Application
    Filed: March 12, 2013
    Publication date: July 25, 2013
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventor: CADENCE DESIGN SYSTEMS, INC.
  • Publication number: 20130097572
    Abstract: Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design.
    Type: Application
    Filed: December 3, 2012
    Publication date: April 18, 2013
    Applicant: Cadence Design Systems, Inc.
    Inventor: Cadence Design Systems, Inc.
  • Publication number: 20130024623
    Abstract: An invention is provided for performing flush cache in a non-volatile memory. The invention includes maintaining a plurality of free memory blocks within a non-volatile memory. When a flush cache command is issued, a flush cache map is examined to obtain a memory address of a memory block in the plurality of free memory blocks within the non-volatile memory. The flush cache map includes a plurality of entries, each entry indicating a memory block of the plurality of free memory blocks. Then, a cache block is written to a memory block at the obtained memory address within the non-volatile memory. In this manner, when a flush cache command is received, the flush cache map allows cache blocks to be written to free memory blocks in the non-volatile memory without requiring a non-volatile memory search for free blocks or requiring erasing of memory blocks storing old data.
    Type: Application
    Filed: September 28, 2012
    Publication date: January 24, 2013
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Cadence Design Systems, Inc.