Patents by Inventor Caesar Cheuk-Chow Cheung
Caesar Cheuk-Chow Cheung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11500780Abstract: The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into subsets of logical addresses. Each of the subsets of logical addresses is assigned to respective processor cores in the data storage system. Each of the processor cores is configured to check each logical address of the assigned subset of logical addresses in the mapping table for a valid physical address mapped to the logical address, for each valid physical address mapped to a logical address of the assigned subset of logical addresses, increment a validity count in a local validity table associated with a blockset of the non-volatile memory corresponding to the valid physical address, and update validity counts in a global validity table associated with respective blocksets of the non-volatile memory with the validity counts in the local validity table.Type: GrantFiled: October 30, 2020Date of Patent: November 15, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Caesar Cheuk-Chow Cheung, Haining Liu, Subhash Balakrishna Pillai
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Publication number: 20210049106Abstract: The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into subsets of logical addresses. Each of the subsets of logical addresses is assigned to respective processor cores in the data storage system. Each of the processor cores is configured to check each logical address of the assigned subset of logical addresses in the mapping table for a valid physical address mapped to the logical address, for each valid physical address mapped to a logical address of the assigned subset of logical addresses, increment a validity count in a local validity table associated with a blockset of the non-volatile memory corresponding to the valid physical address, and update validity counts in a global validity table associated with respective blocksets of the non-volatile memory with the validity counts in the local validity table.Type: ApplicationFiled: October 30, 2020Publication date: February 18, 2021Inventors: Caesar Cheuk-Chow CHEUNG, Haining LIU, Subhash Balakrishna PILLAI
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Patent number: 10846238Abstract: The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into subsets of logical addresses. Each of the subsets of logical addresses is assigned to respective processor cores in the data storage system. Each of the processor cores is configured to check each logical address of the assigned subset of logical addresses in the mapping table for a valid physical address mapped to the logical address, for each valid physical address mapped to a logical address of the assigned subset of logical addresses, increment a validity count in a local validity table associated with a blockset of the non-volatile memory corresponding to the valid physical address, and update validity counts in a global validity table associated with respective blocksets of the non-volatile memory with the validity counts in the local validity table.Type: GrantFiled: June 27, 2019Date of Patent: November 24, 2020Assignee: Western Digital Technologies, Inc.Inventors: Caesar Cheuk-Chow Cheung, Haining Liu, Subhash Balakrishna Pillai
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Publication number: 20190317700Abstract: The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into subsets of logical addresses. Each of the subsets of logical addresses is assigned to respective processor cores in the data storage system. Each of the processor cores is configured to check each logical address of the assigned subset of logical addresses in the mapping table for a valid physical address mapped to the logical address, for each valid physical address mapped to a logical address of the assigned subset of logical addresses, increment a validity count in a local validity table associated with a blockset of the non-volatile memory corresponding to the valid physical address, and update validity counts in a global validity table associated with respective blocksets of the non-volatile memory with the validity counts in the local validity table.Type: ApplicationFiled: June 27, 2019Publication date: October 17, 2019Inventors: Caesar Cheuk-Chow CHEUNG, Haining LIU, Subhash Balakrishna PILLAI
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Patent number: 10380028Abstract: The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into subsets of logical addresses. Each of the subsets of logical addresses is assigned to respective processor cores in the data storage system. Each of the processor cores is configured to check each logical address of the assigned subset of logical addresses in the mapping table for a valid physical address mapped to the logical address, for each valid physical address mapped to a logical address of the assigned subset of logical addresses, increment a validity count in a local validity table associated with a blockset of the non-volatile memory corresponding to the valid physical address, and update validity counts in a global validity table associated with respective blocksets of the non-volatile memory with the validity counts in the local validity table.Type: GrantFiled: December 30, 2016Date of Patent: August 13, 2019Assignee: Western Digital Technologies, Inc.Inventors: Caesar Cheuk-Chow Cheung, Haining Liu, Subhash Balakrishna Pillai
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Patent number: 10348605Abstract: A method includes receiving, at an interface of a storage device and from a host device, an electrical signal representative of data. The storage device includes a mass storage device. The method also includes splitting, at the interface, the electrical signal representative of the data into a first data stream and a second data stream, wherein the first data stream is identical to the second data stream. The method also includes sending, from the interface and to a controller of the storage device, the first data stream; and sending, from the interface and to an analyzer integrated within the storage device, the second data stream. The method further includes filtering, by the analyzer, the second data stream to generate debugging data; and sending, by the analyzer and to the host device, at least a portion of the debugging data.Type: GrantFiled: October 28, 2016Date of Patent: July 9, 2019Assignee: Western Digital Technologies, Inc.Inventors: Thomas Patrick Anderson, Jeerun Chan, Caesar Cheuk-Chow Cheung, Daniel Lee Ellis, Michael Harvill
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Publication number: 20180189187Abstract: The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into subsets of logical addresses. Each of the subsets of logical addresses is assigned to respective processor cores in the data storage system. Each of the processor cores is configured to check each logical address of the assigned subset of logical addresses in the mapping table for a valid physical address mapped to the logical address, for each valid physical address mapped to a logical address of the assigned subset of logical addresses, increment a validity count in a local validity table associated with a blockset of the non-volatile memory corresponding to the valid physical address, and update validity counts in a global validity table associated with respective blocksets of the non-volatile memory with the validity counts in the local validity table.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Inventors: Caesar Cheuk-Chow CHEUNG, Haining LIU, Subhash Balakrishna PILLAI
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Publication number: 20180123936Abstract: A method includes receiving, at an interface of a storage device and from a host device, an electrical signal representative of data. The storage device includes a mass storage device. The method also includes splitting, at the interface, the electrical signal representative of the data into a first data stream and a second data stream, wherein the first data stream is identical to the second data stream. The method also includes sending, from the interface and to a controller of the storage device, the first data stream; and sending, from the interface and to an analyzer integrated within the storage device, the second data stream. The method further includes filtering, by the analyzer, the second data stream to generate debugging data; and sending, by the analyzer and to the host device, at least a portion of the debugging data.Type: ApplicationFiled: October 28, 2016Publication date: May 3, 2018Inventors: Thomas Patrick Anderson, Jeerun Chan, Caesar Cheuk-Chow Cheung, Daniel Lee Ellis, Michael Harvill