Abstract: A compute tile is described. The compute tile includes compute engines and a general-purpose (GP processor coupled with the compute engines. Each of the compute engines includes a compute-in-memory (CIM) hardware module. The CIM hardware module is configured to store weights corresponding to a matrix and to perform a vector-matrix multiplication (VMM) for the matrix. The GP processor is configured to control the compute engines, to receive output of the VMM for the matrix from the compute engines, and to perform a nonlinear operation on the output. The compute engines are addressable by data movement initiators. Data may be moved to and/or from the compute engines in data paths that bypass the GP processor.

Abstract: A learning system is described. The learning system includes multiple cores and at least one processor. The cores may perform operations. The processor(s) implement a core selection scheme whereby a subset of the plurality of cores is selected on which at least one operation is to be performed. The processor(s) also implement an operation selection scheme whereby a subset of the operations is selected for each core in the subset of the plurality of cores. Each core in the subset of the plurality cores performs the subset of the operations selected.