Abstract: Systems and methods are disclosed to transfer data between a first bus internal to a system-on-chip (SOC) device and a second bus external to the SOC device, each bus having a plurality of bus segments shared among a plurality of peripheral devices communicating over one or more bus segments. When reading data from a peripheral device, the system packs data by enabling each effected first bus data segment in sequence until requested data is packed; and when writing data to a peripheral device, the system unpacks data by enabling each effected second bus data segment in sequence until requested data is unpacked.

Abstract: A VLC data transfer interface is presented that allows digital data to be packed and assembled according to a format selectable from a number of formats while the data is being transferred to a desired destination.

Abstract: A VLC data transfer interface is presented that allows digital data to be packed and assembled according to a format selectable from a number of formats while the data is being transferred to a desired destination.

Abstract: Systems and methods are disclosed to detect and correct errors in a flash memory using an error correction cache that provides error correction information by accessing data from a physical block number (PBN) of the flash memory; and if a data error occurred, applying error correction information stored in the cache corresponding to the accessed PBN to correct the data error.

Abstract: Systems and methods are disclosed to perform fast discrete cosine transform (DCT) by computing the DCT in five stages using three coefficients, and scaling the outputs using a plurality of scaling coefficients.

Abstract: A VLC data transfer interface is presented that allows digital data to be packed and assembled according to a format selectable from a number of formats while the data is being transferred to a desired destination.

Abstract: Systems and methods are disclosed to detect and correct errors in a flash memory using an error correction cache that provides error correction information by accessing data from a physical block number (PBN) of the flash memory; and if a data error occurred, applying error correction information stored in the cache corresponding to the accessed PBN to correct the data error.

Abstract: Systems and methods are disclosed to detect and correct errors in a flash memory using an error correction cache that provides error correction information by accessing data from a physical block number (PBN) of the flash memory; and if a data error occurred, applying error correction information stored in the cache corresponding to the accessed PBN to correct the data error.

Abstract: Systems and methods are disclosed to detect and correct errors in a flash memory by detecting in hardware an error based on one of three selectable modes of error detection and correction; and correcting the error by executing error correction software corresponding to the selected mode of error detection and correction.

Abstract: A VLC data transfer interface is presented that allows digital data to be packed and assembled according to a format selectable from a number of formats while the data is being transferred to a desired destination.

Abstract: Systems and methods are disclosed to transfer data between a first bus internal to a system-on-chip (SOC) device and a second bus external to the SOC device, each bus having a plurality of bus segments shared among a plurality of peripheral devices communicating over one or more bus segments. When reading data from a peripheral device, the system packs data by enabling each effected first bus data segment in sequence until requested data is packed; and when writing data to a peripheral device, the system unpacks data by enabling each effected second bus data segment in sequence until requested data is unpacked.

Abstract: Systems and methods are disclosed to detect and correct errors in a flash memory using an error correction cache that provides error correction information by accessing data from a physical block number (PBN) of the flash memory; and if a data error occurred, applying error correction information stored in the cache corresponding to the accessed PBN to correct the data error.

Abstract: Systems and methods are disclosed to perform fast discrete cosine transform (DCT) by computing the DCT in five stages using three coefficients, and scaling the outputs using a plurality of scaling coefficients.

Abstract: Systems and methods are disclosed to detect and correct errors in a flash memory by detecting in hardware an error based on one of three selectable modes of error detection and correction; and correcting the error by executing error correction software corresponding to the selected mode of error detection and correction.