Abstract: A wireless charging device and a warning signal generating method are provided in this disclosure. The warning signal generating method includes: determining whether the smart key of the vehicle is in an operating mode according to a wireless unlock signal when a vehicle is turned off; determining whether a door of the vehicle is opened when the smart key is not in the operating mode; determining whether a portable electronic device is on a wireless charging base of the wireless charging device when the door is opened; and generating a warning signal when the portable electronic device is on the wireless charging base.

Abstract: A wireless charging device and a warning signal generating method are provided in this disclosure. The warning signal generating method includes: determining whether the smart key of the vehicle is in an operating mode according to a wireless unlock signal when a vehicle is turned off; determining whether a door of the vehicle is opened when the smart key is not in the operating mode; determining whether a portable electronic device is on a wireless charging base of the wireless charging device when the door is opened; and generating a warning signal when the portable electronic device is on the wireless charging base.

Abstract: The present disclosure relates to the technical field of biometric identification, and in particular, a fingerprint identification apparatus. The fingerprint identification apparatus includes: a substrate, a sensing chip, a first covering layer, and a second covering layer; wherein the sensing chip is arranged on the substrate, the first covering layer is coated over the sensing chip, the second covering layer is coated on an upper surface of the first covering layer, and the second covering layer is an oleophobic and hydrophobic coating. In the fingerprint identification apparatus according to the embodiment of the present disclosure, a hydrophobic and oleophobic coating is arranged on the surface of the fingerprint identification apparatus, where the density of the hydrophobic components is increased and the hydrophobic as well as oleophobic capabilities are enhanced, and thus the fingerprint identification accuracy and fingerprint identification speed in a wet-finger use environment are improved.

Abstract: The present disclosure relates to the technical field of biometric identification, and in particular, a fingerprint identification apparatus. The fingerprint identification apparatus includes: a substrate, a sensing chip, a first covering layer, and a second covering layer; wherein the sensing chip is arranged on the substrate, the first covering layer is coated over the sensing chip, the second covering layer is coated on an upper surface of the first covering layer, and the second covering layer is an oleophobic and hydrophobic coating. In the fingerprint identification apparatus according to the embodiment of the present disclosure, a hydrophobic and oleophobic coating is arranged on the surface of the fingerprint identification apparatus, where the density of the hydrophobic components is increased and the hydrophobic as well as oleophobic capabilities are enhanced, and thus the fingerprint identification accuracy and fingerprint identification speed in a wet-finger use environment are improved.

Abstract: A circuit for improving process robustness of sub-threshold SRAM memory cells serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to PMOS transistors of the sub-threshold SRAM memory cell and substrate of PMOS transistors in the circuit. The circuit includes a detection circuit for threshold voltages of the PMOS transistors and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS transistors in the sub-threshold SRAM memory cell and the PMOS transistors in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS and NMOS transistor resulted from process fluctuations and thereby regulates the threshold voltages of the PMOS transistors, so that the threshold voltages of the PMOS and NMOS transistors match. The circuit improves the noise margin of sub-threshold SRAM memory cells and the process robustness of sub-threshold SRAM memory cells.

Abstract: Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals A and B, and two control terminals CON and CONF. The control terminals control a work mode (work state and pre-charge state) of the compensation circuit. The compensation circuit consists of 7 PMOS transistors and 8 NMOS transistors. In the normal work state, by detecting changes of potential change rate of two signal lines in an original circuit, the noise current compensation circuit automatically enables one end of the original circuit that discharges slowly to discharge a signal more slowly, and enables one end of the original circuit that discharges rapidly to discharge a signal more rapidly, thus eliminating the influence of the noise current on the circuit and providing assistance for correct identification of subsequent circuit signals.

Abstract: Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals A and B, and two control terminals CON and CONF. The control terminals control a work mode (work state and pre-charge state) of the compensation circuit. The compensation circuit consists of 7 PMOS transistors and 8 NMOS transistors. In the normal work state, by detecting changes of potential change rate of two signal lines in an original circuit, the noise current compensation circuit automatically enables one end of the original circuit that discharges slowly to discharge a signal more slowly, and enables one end of the original circuit that discharges rapidly to discharge a signal more rapidly, thus eliminating the influence of the noise current on the circuit and providing assistance for correct identification of subsequent circuit signals.

Abstract: The present invention discloses a circuit for improving process robustness of sub-threshold SRAM memory cells, which serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to the PMOS tube of the sub-threshold SRAM memory cell and the substrate of a PMOS tube in the circuit. The circuit comprises a detection circuit for threshold voltage of PMOS tube and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS tubes in the sub-threshold SRAM memory cell and the substrate voltage of the PMOS tube in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS tubes and NMOS tubes resulted from process fluctuations and thereby regulate the threshold voltages of the PMOS tubes, so that the threshold voltage of PMOS tubes matches the threshold voltage of NMOS tubes.