Abstract: This invention relates to an encapsulating method for sealed and water-proof LED, comprising the following steps: separately weld two leads or three leads onto the two pins of the LED; molding by mould and used for installing the holder of LED; put the LED with lead or various types of ornaments into the holder; buckle the holder; weld the periphery of the buckled holder by ultrasonic machine to form a sealed luminescent light. By means of welding the lead of the luminotron first, putting it into the holder later, and finally sealing it by ultrasonic machine, it can increase the up-to-standard rate and reduce the rejections on the premise of ensuring the sealing effect.

Abstract: This invention relates to LED string lights with multiple source points comprising several connected LEDs, wherein each LED is installed on a holder. A solid transparent component is also installed on the holder covering the LED. Inside such solid transparent component, there are many small air bubbles. Lights sent out from the LED get through these bubbles and refraction occurs to form multiple source points. During the production, air shall be blown into the solid transparent component to create many separate air bubbles therein. Lights from the LED get through these air bubbles and refraction occurs. Each air bubble is like a source point. Therefore, it's easy and effective for this invention to create many source points even in one LED.

Abstract: The utility model discloses a light-permeable pot, which comprises a pot main unit. The foresaid main unit has a bottom and a side wall, and the upper part is an open-end. Part or all of the foresaid side wall of the pot is light-permeable components; by making the walls of the pot with light-permeable components, parts of the luminous tube can be placed in the trunk in the pot when setting string light. After power-on, the light from the luminous tubes in the pot can pass through the light-permeable components of the side walls to achieving better luminous effect and decorative effective of the decorative trees.

Abstract: Described are structures for a device with a controllable dummy layer which can provide a low controllable trigger voltage and can be used as a first triggered device in ESD protection networks. A controllable dummy layer diode is provided which is structured as a butting diode with a dummy polysilicon layer above the butting region. The dummy polysilicon layer functions as an STI block to remove the STI between the n+ and p+ regions of the diode. In one embodiment the diode has the function of a controllable gate with a punchthrough-like-trigger, in which a capacitor-couple circuit couples a portion of the ESD voltage into the gate of the diode to provide a gate voltage.

Abstract: A process for manufacturing a buried oxide layer for use in partial SOI structures is described. The process begins with the etching of deep trenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pinch-off occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of wade whose size and shape are determined by the number and location of the trenches. Application of the process to the manufacture of a partial SOI RFLDMOS structure is also described together with performance data for the resulting device.

Abstract: A process for manufacturing a buried oxide layer for use in partial SOI structures is described. The process begins with the etching of deep tenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pinch-off occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of oxide whose size and shape are determined by the number and location of the trenches.

Abstract: A novel structured for a diode-like PID protection (DLPP) device structure and process are described. An N-well, three associate N+ regions and a P+ region are formed on a P substrate. The DLPP is structured as a butting diode with a polysilicon gate above the butting region. The gate is connected to a metal antenna element and to the zener like trigger element of the device. The N-well functions as a resistor and capacitor buffer between the poly gate and antenna and the substrate. The antenna picks up a portion of the plasma charge to provide a gate voltage. There is an inversion layer or accumulation layer for positive or negative plasma charge formed under the poly gate. The junction of the effective zener diode is found in the interface between the N-type inversion layer and P+, or N+ and P-type accumulation layer. Changing the shape and the size of the antenna changes the gate voltage, and subsequently the trigger voltage of the DLPP.

Abstract: Described are structures for a device with a controllable dummy layer which can provide a low controllable trigger voltage and can be used as a first triggered device in ESD protection networks. A controllable dummy layer diode is provided which is structured as a butting diode with a dummy polysilicon layer above the butting region. The dummy polysilicon layer functions as an STI block to remove the STI between the n+ and p+ regions of the diode. In one embodiment the diode has the function of a controllable gate with a punchthrough-like-trigger, in which a capacitor-couple circuit couples a portion of the ESD voltage into the gate of the diode to provide a gate voltage.

Abstract: Described are structures for a device with a controllable dummy layer which can provide a low controllable trigger voltage and can be used as a first triggered device in ESD protection networks. A controllable dummy layer diode is provided which is structured as a butting diode with a dummy polysilicon layer above the butting region. The dummy polysilicon layer functions as an STI block to remove the STI between the n+ and p+ regions of the diode. In one embodiment the diode has the function of a controllable gate with a punchthrough-like-trigger, in which a capacitor-couple circuit couples a portion of the ESD voltage into the gate of the diode to provide a gate voltage. By changing the channel length under the gate of the diode as well as the gate voltage, the reverse-biased voltage of the diode is readily adjusted to a predetermined level. In a second embodiment the p+ region of the diode overlaps the n+ region turning the diode into a zener diode.

Abstract: A new method of forming a thick oxide MOS transistor for electrostatic discharge protection in a standard sub-micron STI CMOS process for an integrated circuit device has been achieved. A first well and a second well are implanted. The wells are counter-doped to the substrate type. The first well forms the drain, and the second well forms the source. A thin oxide layer is formed. A polysilicon layer is deposited. The polysilicon layer is patterned to form a dummy floating gate. Ions are implanted into the first well to form a first lightly-doped region and into the second well to form a second lightly-doped region of the same type as the wells. The lightly-doped regions are self-aligned to the dummy floating gate. Sidewall spacers are formed on the floating dummy gates. Ions are implanted into the first well to form a first heavily-doped region and the second well to to form a second heavily-doped region of the same type as the wells. The heavily-doped regions are self-aligned to the sidewall spacers.