Patents by Inventor Cai Lu
Cai Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942324Abstract: A method of promoting adhesion between a dielectric layer of a semiconductor device and a metal fill deposited within a trench in the dielectric layer, including performing an ion implantation process wherein an ion beam formed of an ionized dopant species is directed into the trench at an acute angle relative to a top surface of the dielectric layer to form an implantation layer in a sidewall of the trench, and depositing a metal fill in the trench atop an underlying bottom metal layer, wherein the metal fill adheres to the sidewall.Type: GrantFiled: June 10, 2020Date of Patent: March 26, 2024Assignee: Applied Materials, Inc.Inventors: Qintao Zhang, Jun-Feng Lu, Ting Cai, Ma Ning, Weiye He, Jian Kang
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Patent number: 10305469Abstract: An input/output circuit includes a first switch element, a control voltage providing circuit and a floating voltage providing circuit. The first switch element includes a control terminal, a first path terminal, a second path terminal and a base terminal. The first path terminal receive a first voltage, and the second path terminal receives a second voltage. The control voltage providing circuit provides a control voltage to the control terminal of the first switch element. The floating voltage providing circuit provides the larger between the first voltage and the second voltage to the base terminal of the first switch element, so as to prevent a leakage current from being generated between the first voltage source or the second voltage source and the base terminal of the first switch element.Type: GrantFiled: July 5, 2018Date of Patent: May 28, 2019Assignee: MSTAR SEMICONDUCTOR, INC.Inventor: Wen cai Lu
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Publication number: 20190068183Abstract: An input/output circuit includes a first switch element, a control voltage providing circuit and a floating voltage providing circuit. The first switch element includes a control terminal, a first path terminal, a second path terminal and a base terminal. The first path terminal receive a first voltage, and the second path terminal receives a second voltage. The control voltage providing circuit provides a control voltage to the control terminal of the first switch element. The floating voltage providing circuit provides the larger between the first voltage and the second voltage to the base terminal of the first switch element, so as to prevent a leakage current from being generated between the first voltage source or the second voltage source and the base terminal of the first switch element.Type: ApplicationFiled: July 5, 2018Publication date: February 28, 2019Inventor: Wen cai Lu
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Patent number: 10168385Abstract: An eye pattern measurement apparatus includes: an eye pattern monitoring device, performing first sampling on a data signal by sequentially using scan clock signals having different phases to obtain a plurality of scan data signals; and a data aligning device, connected to the eye pattern monitoring device, receiving the scan data signals outputted by the eye pattern monitoring device, performing phase-shift on the first clock signal to generate a synchronization clock signal, synchronizing the scan data signals with the synchronization clock signal, and outputting the synchronized scan data signals.Type: GrantFiled: September 13, 2017Date of Patent: January 1, 2019Assignee: MSTAR SEMICONDUCTOR, INC.Inventors: Wen cai Lu, Hu Xiao
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Patent number: 10114072Abstract: A processing method and electronic apparatus for a digital signal are provided. The method includes: detecting the quality of a first eye in an eye diagram of the digital signal; equalizing the digital signal; detecting the quality of a second eye in the eye diagram of the equalized digital signal; determining whether the quality of the second eye superior to the quality of the first eye by a predetermined threshold; and if so, outputting the digital signal, or else again equalizing and performing subsequent steps on the auto-compensated digital signal. The above solution is capable of effectively improving the quality of eyes in the eye diagram of the digital signal.Type: GrantFiled: August 17, 2017Date of Patent: October 30, 2018Assignee: MSTAR SEMICONDUCTOR, INC.Inventors: Yuan Yuan, Wen cai Lu
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Publication number: 20180080985Abstract: A processing method and electronic apparatus for a digital signal are provided. The method includes: detecting the quality of a first eye in an eye diagram of the digital signal; equalizing the digital signal; detecting the quality of a second eye in the eye diagram of the equalized digital signal; determining whether the quality of the second eye superior to the quality of the first eye by a predetermined threshold; and if so, outputting the digital signal, or else again equalizing and performing subsequent steps on the auto-compensated digital signal. The above solution is capable of effectively improving the quality of eyes in the eye diagram of the digital signal.Type: ApplicationFiled: August 17, 2017Publication date: March 22, 2018Inventors: Yuan Yuan, Wen cai Lu
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Publication number: 20180083604Abstract: An eye pattern measurement apparatus includes: an eye pattern monitoring device, performing first sampling on a data signal by sequentially using scan clock signals having different phases to obtain a plurality of scan data signals; and a data aligning device, connected to the eye pattern monitoring device, receiving the scan data signals outputted by the eye pattern monitoring device, performing phase-shift on the first clock signal to generate a synchronization clock signal, synchronizing the scan data signals with the synchronization clock signal, and outputting the synchronized scan data signals.Type: ApplicationFiled: September 13, 2017Publication date: March 22, 2018Inventors: Wen cai Lu, Hu Xiao
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Patent number: 9780979Abstract: A analog equalizer includes: an adjusting circuit, generating an adjustment signal and a selection signal; a cascaded equalization circuit, receiving the adjustment signal, and adjusting at least one of a tunable resistor, a tunable capacitor and a tunable current source in the multi-stage equalization circuit according to the adjustment signal to perform an equalization process on a signal to be equalized; and an analog multiplexer, coupled to the cascaded equalization circuit and the adjusting circuit, selecting and outputting an equalized signal outputted from one stage of the multi-stage equalization circuit according to the selection signal. Wherein, the adjusting circuit adjusts the adjustment signal and the selection signal according to the equalized signal outputted from the analog multiplexer and a target equalization value.Type: GrantFiled: January 23, 2017Date of Patent: October 3, 2017Assignee: MSTAR SEMICONDUCTOR, INC.Inventors: Kai Sun, Jiunn-Yih Lee, Wen-Cai Lu
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Publication number: 20170222848Abstract: A analog equalizer includes: an adjusting circuit, generating an adjustment signal and a selection signal; a cascaded equalization circuit, receiving the adjustment signal, and adjusting at least one of a tunable resistor, a tunable capacitor and a tunable current source in the multi-stage equalization circuit according to the adjustment signal to perform an equalization process on a signal to be equalized; and an analog multiplexer, coupled to the cascaded equalization circuit and the adjusting circuit, selecting and outputting an equalized signal outputted from one stage of the multi-stage equalization circuit according to the selection signal. Wherein, the adjusting circuit adjusts the adjustment signal and the selection signal according to the equalized signal outputted from the analog multiplexer and a target equalization value.Type: ApplicationFiled: January 23, 2017Publication date: August 3, 2017Inventors: Kai Sun, Jiunn-Yih Lee, Wen-Cai Lu
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Patent number: 8564340Abstract: A dual phase-locked loop (PLL) circuit includes a phase/frequency detector, a charge pump, a frequency tuning circuit and an N divider. The frequency tuning circuit includes a coarse-tuning circuit, for coarse-tuning an output frequency of the dual PLL circuit to approximate a target frequency; a fine-tuning circuit, for fine-tuning the output frequency of the dual PLL circuit to the target frequency; and a current control oscillator (CCO), for generating an output signal of the dual PLL circuit. The output frequency of the output signal is equal to the target frequency.Type: GrantFiled: June 29, 2010Date of Patent: October 22, 2013Assignee: MStar Semiconductor, Inc.Inventors: Yong-Wang Liu, Wen-cai Lu, Sterling Smith
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Publication number: 20120166160Abstract: A block model constructing method for complex geological structures is provided. The method comprises the following steps: a) making a triangle mesh description of a layer plane or a fault plane; b) judging whether two triangles intersect, and finding out the intersection points if they intersect; c) performing a geometric consistency and topological consistency processing within every intersectant triangle; d) extracting an enclosing block to acquire an interface constituted of peripheral edges of the enclosing block, and defining a geological attribute of the enclosing block to form a three-dimensional model block. The method needs not to solve difficult equation sets with large computation, thus simplifying the constructing method.Type: ApplicationFiled: February 2, 2010Publication date: June 28, 2012Applicant: China National Petroleum CorporationInventors: Zhengxi Tao, Cai Lu, Hong Liu, Chen Zhu, Longjiang Jing, Zhen Li
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Patent number: 7884378Abstract: An LED package structure includes a frame, at least a first LED, and at least a second LED. The frame includes a base having a first cavity and a second cavity, where the second cavity is disposed under the first cavity and the second cavity is smaller than the first cavity. The first LED is disposed in the bottom of the first cavity, and the second LED is disposed in the bottom of the second cavity.Type: GrantFiled: October 26, 2009Date of Patent: February 8, 2011Assignee: Chunghwa Picture Tubes, Ltd.Inventors: Fu-Cai Lu, Chun-Wei Su, Chien-Lung Tsou, Chi-Neng Mo
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Publication number: 20110024773Abstract: An LED package structure includes a frame, at least a first LED, and at least a second LED. The frame includes a base having a first cavity and a second cavity, where the second cavity is disposed under the first cavity and the second cavity is smaller than the first cavity. The first LED is disposed in the bottom of the first cavity, and the second LED is disposed in the bottom of the second cavity.Type: ApplicationFiled: October 26, 2009Publication date: February 3, 2011Inventors: Fu-Cai Lu, Chun-Wei Su, Chien-Lung Tsou, Chi-Neng Mo
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Publication number: 20110006820Abstract: A dual phase-locked loop (PLL) circuit includes a phase/frequency detector, a charge pump, a frequency tuning circuit and an N divider. The frequency tuning circuit includes a coarse-tuning circuit, for coarse-tuning an output frequency of the dual PLL circuit to approximate a target frequency; a fine-tuning circuit, for fine-tuning the output frequency of the dual PLL circuit to the target frequency; and a current control oscillator (CCO), for generating an output signal of the dual PLL circuit. The output frequency of the output signal is equal to the target frequency.Type: ApplicationFiled: June 29, 2010Publication date: January 13, 2011Applicant: MSTAR SEMICONDUCTOR, INC.Inventors: Yong-Wang Liu, Wen-cai Lu, Sterling Smith
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Patent number: 7795937Abstract: A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal.Type: GrantFiled: March 12, 2009Date of Patent: September 14, 2010Assignee: MStar Semiconductor, Inc.Inventors: Sterling Smith, Ellen Chen Yeh, Wen cai Lu
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Publication number: 20090243679Abstract: A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal.Type: ApplicationFiled: March 12, 2009Publication date: October 1, 2009Applicant: MSTAR SEMICONDUCTOR, INC.Inventors: Sterling Smith, Ellen Chen Yeh, Wen cai Lu