Patents by Inventor Caineng Huo

Caineng Huo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240078942
    Abstract: A display module includes a substrate, m rows and n columns of pad sets, m*n sets of light emitting chip sets and multiple pins. The substrate includes a first surface and a second surface disposed opposite to each other. Each set of pad sets among the m rows and n columns of pad sets includes three pairs of pads, and first pads in the each set of pad sets are electrically connected. In a same set of light emitting chips, each of first electrodes of the light emitting chips is connected to a respective one of first pads of one set of pad sets among the m rows and n columns of pad sets, and each of second electrodes of the light emitting chips is connected to a respective one of second pads of a same set of pad sets.
    Type: Application
    Filed: April 27, 2023
    Publication date: March 7, 2024
    Applicant: FOSHAN NATIONSTAR OPTOELECTRONICS CO., LTD.
    Inventors: Kuai QIN, Heng GUO, Shaojia XIE, Bin CAI, Caineng HUO, Kailiang FAN
  • Publication number: 20240006572
    Abstract: A LED display unit group includes a substrate and an electronic device, where the substrate includes a pad layer, an ink layer and an identification structure, the pad layer is disposed on a first surface of a side of the substrate adjacent to the electronic device; the pad layer includes pad regions and a non-pad region, each of the pad regions includes multiple pads, and the non-pad region includes metal traces; and the ink layer is disposed above the pad layer; each of the multiple pads is configured to secure the electronic device and is electrically connected to the electronic device; the metal traces are configured to connect the multiple pads via the metal traces; and an orthographic projection of the identification structure on the substrate is partially overlapped or staggered with an orthographic projection of the pad regions on the substrate.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 4, 2024
    Applicant: FOSHAN NATIONSTAR OPTOELECTRONICS CO., LTD.
    Inventors: Kuai QIN, Shaojia XIE, Bin CAI, Fangping HE, Zhuang PENG, Caineng HUO
  • Publication number: 20230029972
    Abstract: A manufacturing method for an integrated chip is used for forming and processing an electrode structure of the integrated chip. The method includes step S1 and step S2. In step S1, a light-emitting portion is manufactured, and the light-emitting portion includes multiple light-emitting unit groups distributed in the form of a matrix. In step S2, conductive terminals multiple first electrodes and conductive terminals of multiple second electrodes of the light-emitting portion are electrically led out to form multiple first pin electrodes and multiple second pin electrodes. The first pin electrodes and the second pin electrodes are used for being electrically connected to a circuit substrate.
    Type: Application
    Filed: December 18, 2020
    Publication date: February 2, 2023
    Applicant: FOSHAN NATIONSTAR OPTOELECTRONICS CO., LTD.
    Inventors: Kuai Qin, Heng Guo, Kailiang Fan, Caineng Huo, Zhuang Peng