Abstract: Methods, systems, and devices for memory block utilization in memory systems are described. A system configured to allow a memory device to group or segment a memory block into two or more sub-memory blocks, which can be independently programmed is described herein. For example, a host system may determine a configuration of a memory array, and communicate the configuration information to the memory system, and transmit a command for an operation to the memory system. In some examples, the memory system may utilize the memory array configuration information and determine to segment the blocks of memory cells into sub-blocks. By segmenting the memory block into sub-blocks, the memory device may maintain its memory block density while supporting efficient programming of blocks of the memory array.

Abstract: Methods, systems, and devices for critical data management within a memory system are described. A memory system may avoid writing critical data to weak word lines. For example, as part of a media management operation or a host write operation (among other examples), the memory system may determine which data is critical data and may determine which word lines are weak word lines, which may refer to word lines having bit error rates that satisfy a threshold. The memory system may refrain from writing critical data to memory cells coupled with weak word lines, and may instead write non-critical or dummy data to the weak word lines. The memory system may reserve the writing of critical data to memory cells coupled with non-weak word lines, which may refer to word lines having bit error rates that fail to satisfy the threshold.

Abstract: Methods, systems, and devices for assigning blocks of memory systems are described. Some memory systems may be configured to initiate an operation to characterize a plurality of blocks of a memory system; identify a first quantity of complete blocks of the plurality of blocks and a second quantity of reduced blocks of the plurality of blocks based at least in part on initiating the operation; determine, for a block of the second quantity of reduced blocks, whether a quantity of planes available for use to store the information in the block satisfies a threshold; and assign the block as a special function block configured to store data associated with a function of the memory system based at least in part on determining that the quantity of planes available for use to store the information in the block of the second quantity of reduced blocks satisfies the threshold.

Abstract: Methods, systems, and devices for partial block allocations for memory systems are described. A memory system may allocate partial blocks of a memory device for storage of data. In some examples, one or more full blocks across a set of layers of the memory device may be allocated for data storage. Additionally, one or more partial blocks across a subset of the set of layers of the memory device may be allocated for data storage, such as user data or system data. Accordingly, a total utilization of the memory may be increased, thereby increasing the overall capacity of the memory device. As such, the memory system may provide additional storage for a user or additional storage for supporting memory system operations, including overprovisioning for garbage collection or error correction operations.

Abstract: Methods, systems, and devices for memory page type indications for data integrity evaluations are described. A memory system may verify a page type corresponding to read data. For example, the memory system may store an indication of a page type corresponding to data written to memory cells as one or more bits of the data. During a read operation, the memory system may compare the stored indication of the page type to a second indication of a page type for data intended to be read. For example, the first indication read from the memory cells may correspond to a first page type, and the second indication (e.g., from an address mapping table, from metadata) may indicate a second page type. If the first and second indications are different, the memory system may refrain from outputting the data and may instead indicate an error or perform a second read operation.

Abstract: Methods, systems, and devices for cache techniques for memory system read commands are described. A memory device of a memory system may reduce latency associated with cache access operations based on receiving a multi-plane command from the memory system. For example, the memory system may transmit an access command that indicates (e.g., using one or more bits, via a prefix associated with the command) that an access operation is for a multi-plane read of the memory device. The memory device may transfer data from a first cache of the memory device to a second cache of the memory device prior to receiving each address indication for the access operation. As such, the memory device may concurrently perform the transfer of the data with the receiving of at least one address indication, thereby reducing latency associated with the access operation and response times of the memory system.

Abstract: Methods, systems, and devices for configurable low voltage detection threshold at a memory system are described. The described techniques provide for a memory system to adjust a low voltage detection (LVD) threshold according to an interface speed of the memory system. The LVD threshold may be correlated with the interface speed, such that when operating at a relatively high interface speed, the memory system may set the LVD threshold to a relatively high value and when operating at a relatively low interface speed, the memory system may set the LVD threshold to a relatively low value. Additionally, or alternatively, the memory system may be configured to adjust the LVD threshold when changing an interface speed for subsequent operations. For example, the memory system may receive a command indicating a second interface speed and may set the LVD threshold to a second value that is associated with the second speed.

Abstract: Methods, systems, and devices for independent source clocks for memory access operations are described. A memory system may be configured to support a multi-source clock scheme that utilizes independent source clocks for read data transfers and write data transfers across an interface. Based on performing the read operations, the memory system may communicate read data over a channel using a first source clock operating at a first frequency. The memory system may communicate write data over the channel using a second source clock operating at a second frequency. Based on communicating the write data, the memory system may perform one or more write operations.

Abstract: Methods, systems, and devices for critical data management within a memory system are described. A memory system may avoid writing critical data to weak word lines. For example, as part of a media management operation or a host write operation (among other examples), the memory system may determine which data is critical data and may determine which word lines are weak word lines, which may refer to word lines having bit error rates that satisfy a threshold. The memory system may refrain from writing critical data to memory cells coupled with weak word lines, and may instead write non-critical or dummy data to the weak word lines. The memory system may reserve the writing of critical data to memory cells coupled with non-weak word lines, which may refer to word lines having bit error rates that fail to satisfy the threshold.

Abstract: Methods, apparatuses and systems related to managing stored data in view of charge losses are described. An apparatus may include a management mechanism that scans memory cells and adjusts read voltage levels for the memory cells to account for charge losses during operation of the apparatus. The apparatus may further leverage the management mechanism to detect or estimate one or more targeted conditions by tracking an adjustment progress while implementing the management mechanism. When the adjustment progress reaches a predetermined condition, the apparatus can estimate the occurrence of the one or more targeted conditions and implement a data refresh mechanism to restore the charges to their intended levels instead of completing the management mechanism.

Abstract: A memory sub-system to initiate an erase operation to erase a first set of memory cells of a first memory block of a first memory plane and a second set of memory cells of a second memory block of a second memory plane of a memory device. A set of erase pulses of the erase operation are caused to be applied to the first set of memory cells of the first memory block and the second set of memory cells of the second memory block concurrently. One or more erase verify sub-operations of the erase operation are executed to verify the first set of memory cells and the second set of memory cells are erased.

Abstract: Apparatuses, media, and methods associated with providing guidance while performing tasks are described. Guidance can be provided in the form of directions for reaching a destination. For example, the guidance can include determining a destination and/or providing directions to reach the destination in the least amount of time. The guidance can include directions in the form of audible turn by turn instructions, a route shown on a map, and/or indications by streetlights or street signs (e.g., the route to the destination is indicated by flashing streetlights or words shown on street signs), among other types of guidance. Guidance can be provided in the form of instructions for performing a task. For example, the guidance can include instructions for treating a medical condition of an individual in an ambulance.

Abstract: Methods, systems, and devices for suspension during a multi-plane write procedure are described. A memory system may perform a multi-plane write procedure by writing to a set of planes in parallel. Upon detecting a defective plane in the set of planes, the memory system may suspend writing to the defective plane until writing to the other planes in the set of planes is finished. The memory system may then resume writing to the defective plane.

Abstract: The present disclosure provides a battery pack and a vehicle capable of improving safety. A battery pack includes: a housing including a bottom plate, the bottom plate being provided with an accommodating portion; battery modules arranged above the bottom plate and including first battery modules and second battery modules, with a gap between the first battery modules and the second battery modules that overlaps with the accommodating portion when viewed in the up-down direction; a control device configured in the gap; a low-voltage connection assembly electrically connecting the battery modules and the control device and configured in the gap; and a high-voltage connection assembly electrically connecting the battery modules and accommodated in the accommodating portion.

Abstract: A memory sub-system to initiate an erase operation to erase a first set of memory cells of a first memory block and a second set of memory cells of a second memory block of a memory device. One or more erase pulses of the erase operation are caused to be applied to the first set of memory cells of the first memory block and the second set of memory cells of the second memory block concurrently. A first erase verify sub-operation of the erase operation is caused to be performed to verify the first memory block is erased and a second erase verify sub-operation of the erase operation is caused to be performed to verify the second memory block is erased.

Abstract: Methods, systems, and devices for memory block utilization in memory systems are described. A system configured to allow a memory device to group or segment a memory block into two or more sub-memory blocks, which can be independently programmed is described herein. For example, a host system may determine a configuration of a memory array, and communicate the configuration information to the memory system, and transmit a command for an operation to the memory system. In some examples, the memory system may utilize the memory array configuration information and determine to segment the blocks of memory cells into sub-blocks. By segmenting the memory block into sub-blocks, the memory device may maintain its memory block density while supporting efficient programming of blocks of the memory array.

Abstract: A system for electronically and optically monitoring biological samples, the system including: a multi-well plate having a plurality of wells configured to receive a plurality of biological samples, each of the wells having a set of electrodes and a transparent window on a bottom surface of the well that is free of electrodes; an illumination module configured to illuminate the wells; a cradle configured to receive the multi-well plate, the cradle having an opening on the bottom that exposes the transparent windows of the wells; and an optical imaging module movable across different wells of a same multi-well plate to capture images through the windows.

Abstract: A memory device includes a memory array configured as quad-level cell (QLC) memory and a control logic operatively coupled to the memory array. The control logic identifies a first two bits of particular pages of a QLC logical state. The control logic causes memory cells of the memory array to be coarse programmed with a threshold voltage distribution of a multi-level cell (MLC) logical state corresponding to the first two bits. The control logic reads the MLC logical state from the memory cells and a second two bits from a cache buffer to determine the QLC logical state. The control logic causes the memory cells to be further coarse programmed with a QLC threshold voltage distribution corresponding to the QLC logical state.

Abstract: Methods, systems, and devices for assigning blocks of memory systems are described. Some memory systems may be configured to initiate an operation to characterize a plurality of blocks of a memory system; identify a first quantity of complete blocks of the plurality of blocks and a second quantity of reduced blocks of the plurality of blocks based at least in part on initiating the operation; determine, for a block of the second quantity of reduced blocks, whether a quantity of planes available for use to store the information in the block satisfies a threshold; and assign the block as a special function block configured to store data associated with a function of the memory system based at least in part on determining that the quantity of planes available for use to store the information in the block of the second quantity of reduced blocks satisfies the threshold.

Abstract: Methods, systems, and devices for memory block utilization in memory systems are described. A system configured to allow a memory device to group or segment a memory block into two or more sub-memory blocks, which can be independently programmed is described herein. For example, a host system may determine a configuration of a memory array, and communicate the configuration information to the memory system, and transmit a command for an operation to the memory system. In some examples, the memory system may utilize the memory array configuration information and determine to segment the blocks of memory cells into sub-blocks. By segmenting the memory block into sub-blocks, the memory device may maintain its memory block density while supporting efficient programming of blocks of the memory array.