Abstract: Silicon carbide (SiC) materials including SiC wafers and SiC boules and related methods are disclosed that provide large dimension SiC wafers with reduced crystallographic stress. Growth conditions for SiC materials include maintaining a generally convex growth surface of SiC crystals, adjusting differences in front-side to back-side thermal profiles of growing SiC crystals, supplying sufficient source flux to allow commercially viable growth rates for SiC crystals, and reducing the inclusion of contaminants or non-SiC particles in SiC source materials and corresponding SiC crystals. By forming larger dimension SiC crystals that exhibit lower crystallographic stress, overall dislocation densities that are associated with missing or additional planes of atoms may be reduced, thereby improving crystal quality and usable SiC crystal growth heights.

Abstract: Silicon carbide (SiC) wafers and related methods are disclosed that include large diameter SiC wafers with wafer shape characteristics suitable for semiconductor manufacturing. Large diameter SiC wafers are disclosed that have reduced deformation related to stress and strain effects associated with forming such SiC wafers. As described herein, wafer shape and flatness characteristics may be improved by reducing crystallographic stress profiles during growth of SiC crystal boules or ingots. Wafer shape and flatness characteristics may also be improved after individual SiC wafers have been separated from corresponding SiC crystal boules. In this regard, SiC wafers and related methods are disclosed that include large diameter SiC wafers with suitable crystal quality and wafer shape characteristics including low values for wafer bow, warp, and thickness variation.

Abstract: Silicon carbide (SiC) materials including SiC wafers and SiC boules and related methods are disclosed that provide large dimension SiC wafers with reduced crystallographic stress. Growth conditions for SiC materials include maintaining a generally convex growth surface of SiC crystals, adjusting differences in front-side to back-side thermal profiles of growing SiC crystals, supplying sufficient source flux to allow commercially viable growth rates for SiC crystals, and reducing the inclusion of contaminants or non-SiC particles in SiC source materials and corresponding SiC crystals. By forming larger dimension SiC crystals that exhibit lower crystallographic stress, overall dislocation densities that are associated with missing or additional planes of atoms may be reduced, thereby improving crystal quality and usable SiC crystal growth heights.

Abstract: Silicon carbide (SiC) wafers and related methods are disclosed that include large diameter SiC wafers with wafer shape characteristics suitable for semiconductor manufacturing. Large diameter SiC wafers are disclosed that have reduced deformation related to stress and strain effects associated with forming such SiC wafers. As described herein, wafer shape and flatness characteristics may be improved by reducing crystallographic stress profiles during growth of SiC crystal boules or ingots. Wafer shape and flatness characteristics may also be improved after individual SiC wafers have been separated from corresponding SiC crystal boules. In this regard, SiC wafers and related methods are disclosed that include large diameter SiC wafers with suitable crystal quality and wafer shape characteristics including low values for wafer bow, warp, and thickness variation.

Abstract: Group III nitride light emitting diode (LED) structures with improved electrical performance are disclosed. A Group III nitride LED structure includes one or more n-type layers, one or more p-type layers, and an active region that includes a plurality of sequentially arranged barrier-well units. In certain embodiments, doping profiles of barrier layers of the barrier-well units are configured such that a doping concentration in some barrier-well units is different than a doping concentration in other barrier-well units. In certain embodiments, a doping profile of a particular barrier layer is non-uniform. In addition to active region configurations, the doping profiles and sequence of the n-type layers and p-type layers are configured to provide Group III nitride structures with higher efficiency, lower forward voltages, and improved forward voltage performance at elevated currents and temperatures.

Abstract: Silicon carbide (SiC) materials including SiC wafers and SiC boules and related methods are disclosed that provide large dimension SiC wafers with reduced crystallographic stress. Growth conditions for SiC materials include maintaining a generally convex growth surface of SiC crystals, adjusting differences in front-side to back-side thermal profiles of growing SiC crystals, supplying sufficient source flux to allow commercially viable growth rates for SiC crystals, and reducing the inclusion of contaminants or non-SiC particles in SiC source materials and corresponding SiC crystals. By forming larger dimension SiC crystals that exhibit lower crystallographic stress, overall dislocation densities that are associated with missing or additional planes of atoms may be reduced, thereby improving crystal quality and usable SiC crystal growth heights.

Abstract: Silicon carbide (SiC) wafers and related methods are disclosed that include large diameter SiC wafers with wafer shape characteristics suitable for semiconductor manufacturing. Large diameter SiC wafers are disclosed that have reduced deformation related to stress and strain effects associated with forming such SiC wafers. As described herein, wafer shape and flatness characteristics may be improved by reducing crystallographic stress profiles during growth of SiC crystal boules or ingots. Wafer shape and flatness characteristics may also be improved after individual SiC wafers have been separated from corresponding SiC crystal boules. In this regard, SiC wafers and related methods are disclosed that include large diameter SiC wafers with suitable crystal quality and wafer shape characteristics including low values for wafer bow, warp, and thickness variation.

Abstract: Group III nitride light emitting diode (LED) structures with improved electrical performance are disclosed. A Group III nitride LED structure includes one or more n-type layers, one or more p-type layers, and an active region that includes a plurality of sequentially arranged barrier-well units. In certain embodiments, doping profiles of barrier layers of the barrier-well units are configured such that a doping concentration in some barrier-well units is different than a doping concentration in other barrier-well units. In certain embodiments, a doping profile of a particular barrier layer is non-uniform. In addition to active region configurations, the doping profiles and sequence of the n-type layers and p-type layers are configured to provide Group III nitride structures with higher efficiency, lower forward voltages, and improved forward voltage performance at elevated currents and temperatures.