Patents by Inventor Calist Friedman

Calist Friedman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device with backside inductor using through silicon vias
    Patent number: 11101211
    Abstract: An approach to creating a semiconductor chip including a semiconductor substrate with one or more topside metal layers and one or more backside metal layers. The approach creates the semiconductor chip with one or more semiconductor devices with wiring interconnects in the one or more topside metal layers on the semiconductor substrate and one or more inductors in the one or more backside metal layer. Furthermore, the approach creates the semiconductor chip with one or more through silicon vias extending through the semiconductor substrate connecting the one or more inductors in the one or more backside metal layers and the one or more semiconductor devices with wiring interconnects in the one or more topside metal layers on the semiconductor substrate.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Hassan Naser, Calist Friedman, Matthew A. Cooke, Daniel L. Stasiak
  • SEMICONDUCTOR DEVICE WITH BACKSIDE INDUCTOR USING THROUGH SILICON VIAS
    Publication number: 20210098370
    Abstract: An approach to creating a semiconductor chip including a semiconductor substrate with one or more topside metal layers and one or more backside metal layers. The approach creates the semiconductor chip with one or more semiconductor devices with wiring interconnects in the one or more topside metal layers on the semiconductor substrate and one or more inductors in the one or more backside metal layer. Furthermore, the approach creates the semiconductor chip with one or more through silicon vias extending through the semiconductor substrate connecting the one or more inductors in the one or more backside metal layers and the one or more semiconductor devices with wiring interconnects in the one or more topside metal layers on the semiconductor substrate.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 1, 2021
    Inventors: Hassan Naser, Calist Friedman, Matthew A. Cooke, Daniel L. Stasiak