Abstract: Techniques for parsing FPGA counter data records in a network device with an FPGA are provided. In one set of embodiments these techniques include ingesting, by the network device, a metadata file associated with an application image programmed in (or configured to be programmed in) the FPGA, where the metadata file includes definitions of counter data record types that are used (i.e., reported via counter messages) by the application image. The techniques further include receiving a counter message from the FPGA that includes one or more counter data records and, for each record, retrieving the ingested definition of that record's type and parsing the record in accordance with the definition.

Abstract: A method of operating a network device is provided. The method can include obtaining incoming data packets, conveying the incoming data packets through a parallel data bus, and using a demultiplexer to split the incoming data packets being conveyed through the parallel data bus onto a plurality of separate independent data paths within the network device. The method can further include using a multiplexer to aggregate or merge data packets from the plurality of data paths onto an egress parallel data bus.

Abstract: A switching system includes a content-addressable memory (CAM) and several processing nodes. The CAM can be selectively connected to any one or more of the processing nodes during operation of the switching system, without having to power down or otherwise reboot the switching system. The CAM is selectively connected to a processing node in that electrical paths between the CAM and the processing nodes can be established, torn down, and re-established during operation of the switching system. The switching system can include a connection matrix to selectively establish electrical paths between the CAM and the processing nodes.

Abstract: A method and system for emulating physical layer (L1) connectivity between distant computing devices. Existing solutions require that the computing devices or end points directly connect to a same interconnecting (or network) device and/or employ network devices requiring awareness of the communication protocol used between the end points. Further, existing solutions typically fail to match the ingress and egress clock rates. These restrictions limit scaling of the solutions, confine the end points to a physical co-location, and/or fail to transport or replicate the physical properties (e.g., errors, proprietary signaling, clock frequency, etc.) of the data stream transmitted between the end points. The disclosed method and system overcome these limitations through implementation of a L1 connectivity abstraction between computing devices across a network, and through clock rate reconstruction using a data buffer state controlled phase lock loop (PLL) mechanism.

Abstract: A method and system for emulating physical layer (L1) connectivity between distant computing devices. Existing solutions require that the computing devices or end points directly connect to a same interconnecting (or network) device and/or employ network devices requiring awareness of the communication protocol used between the end points. Further, existing solutions typically fail to match the ingress and egress clock rates. These restrictions limit scaling of the solutions, confine the end points to a physical co-location, and/or fail to transport or replicate the physical properties (e.g., errors, proprietary signaling, clock frequency, etc.) of the data stream transmitted between the end points. The disclosed method and system overcome these limitations through implementation of a L1connectivity abstraction between computing devices across a network, and through clock rate reconstruction using a data buffer state controlled phase lock loop (PLL) mechanism.

Abstract: A bitstream representing an Ethernet frame is received over a physical medium. Encoded Ethernet blocks are recovered from the bitstream. The Ethernet blocks are descrambled and provided to downstream switching logic, intact, without removing the synchronization bits that were added during the encoding process. More particularly, the intact descrambled Ethernet block is divided into smaller-sized data words; the size of the data words being an integer multiple of the size of the Ethernet block.

Abstract: A switching system includes a content-addressable memory (CAM) and several processing nodes. The CAM can be selectively connected to any one or more of the processing nodes during operation of the switching system, without having to power down or otherwise reboot the switching system. The CAM is selectively connected to a processing node in that electrical paths between the CAM and the processing nodes can be established, torn down, and re-established during operation of the switching system. The switching system can include a connection matrix to selectively establish electrical paths between the CAM and the processing nodes.

Abstract: A bitstream representing an Ethernet frame is received over a physical medium. Encoded Ethernet blocks are recovered from the bitstream. The Ethernet blocks are descrambled and provided to downstream switching logic, intact, without removing the synchronization bits that were added during the encoding process. More particularly, the intact descrambled Ethernet block is divided into smaller-sized data words; the size of the data words being an integer multiple of the size of the Ethernet block.